DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements 1.3. Generating the DisplayPort Intel® FPGA IP Design Example 1.4. Simulating the Design 1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design x
1.5.1. Regenerating .elf File
2. Parallel Loopback Design Examples x
2.1. Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features 2.4. Enabling Adaptive Sync Support 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameter 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features x
2.3.1. Cyclone® 10 GX DisplayPort SST TX-only Design Features 2.3.2. Cyclone® 10 GX DisplayPort SST RX-only Design Features
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

1.3. Generating the DisplayPort Intel® FPGA IP Design Example

Use the parameter editor in the Quartus® Prime Pro Edition software to generate the design example.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. Open Quartus® Prime.
  2. Click Tools > IP Catalog, and select Cyclone® 10 GX as the target device family.
    Note: The design example only support Cyclone® 10 GX devices.
  3. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP Variation window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip .
  5. Select an Cyclone® 10 GX device in the Device field, or keep the default Quartus® Prime software device selection.
  6. Click OK. The parameter editor appears.
  7. Configure the desired parameters for both TX and RX.
    Note: The Nios® V software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios® V terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  8. On the Design Example tab, select DisplayPort MST Parallel Loopback With PCR, or DisplayPort MST Parallel Loopback Without PCR , DisplayPort SST TX-only, DisplayPort SST RX-only DisplayPort SST Parallel Loopback With PCR, or DisplayPort SST Parallel Loopback Without PCR.
  9. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    Note: DisplayPort MST design examples are supported only in synthesis; they are not supported in simulation.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  10. For Target Development Kit, select Cyclone 10 GX FPGA Development Kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit. For Cyclone 10 GX FPGA Development Kit, the default device is 10CX220YF780E5G.
  11. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.
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