2.5. Design Components
Module | Description |
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Core System (Platform Designer) | The core system consists of the Nios® V Processor and its necessary components, DisplayPort RX and TX core sub-systems. This system provides the infrastructure to interconnect the Nios® V processor with the DisplayPort Intel® FPGA IP (RX and TX instances) through Avalon® memory-mapped interface within a single Platform Designer system to ease the software build flow.
This system consists of:
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RX Sub-System (Platform Designer) |
The RX sub-system consists of:
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TX Sub-System (Platform Designer) |
The TX sub-system consists of:
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Module | Description |
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RX PHY Top |
The RX PHY top level consists of the components related to the receiver PHY layer.
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TX PHY Top |
The TX PHY top level consists of the components related to the transmitter PHY layer.
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Module | Description |
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Transceiver Arbiter | This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations. This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon® memory-mapped RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel. The transceiver arbiter identifies the requester of a reconfiguration through its Avalon® memory-mapped reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly. |
IOPLL | IOPLL generates common source clock: dp_rx_vid_clkout and clk_16 (16 MHz) for the DisplayPort system.
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