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1.1. Directory Structure
1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements
1.3. Generating the DisplayPort Intel® FPGA IP Design Example
1.4. Simulating the Design
1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design
1.6. DisplayPort Intel® FPGA IP Design Example Parameters
2.1. Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features
2.2. Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features
2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features
2.4. Enabling Adaptive Sync Support
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameter
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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2.8. Hardware Setup
The DisplayPort Intel® FPGA IP design example is 4Kp60 capable and performs a loop-through for a standard DisplayPort video stream.
- To run the hardware test, connect a DisplayPort-enabled source device to the DisplayPort FMC daughter card sink input.
- The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core.
- The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data.
Note: You require the clock recovery feature to produce video without using a frame buffer.
- The clock recovery core then sends the video data to the DisplayPort source and the Transceiver Native PHY TX block.
- Connect the DisplayPort FMC daughter card source port to a monitor to display the image.
LEDs | Function |
---|---|
USER_LED[0] | This LED indicates that the source is successfully lane-trained. At this point, the IP core asserts rx0_vid_locked. |
USER_LED[1] | This LED indicates that the source Transceiver PLL is locked at the link training data rate. |
USER_LED[3:2] | These LEDs indicate the RX link rate.
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