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1.1. Directory Structure
1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements
1.3. Generating the DisplayPort Intel® FPGA IP Design Example
1.4. Simulating the Design
1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design
1.6. DisplayPort Intel® FPGA IP Design Example Parameters
2.1. Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features
2.2. Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features
2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features
2.4. Enabling Adaptive Sync Support
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameter
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features
This section describes DisplayPort SST TX-only and RX-only design example variants. Simulation models are not available for TX-only and RX-only designs.