2.10. DisplayPort Transceiver Reconfiguration Flow
The VESA DisplayPort Standard version 1.4 supports 4 link rates (8.1 Gbps, 5.4 Gbps, 2.7 Gbps, and 1.62 Gbps). You can dynamically switch from 1 data rate to another. Transceiver reconfiguration is required to support dynamic link rate switching.
The DisplayPort Intel® FPGA IP design examples require some level of reconfiguration and recalibration but with some modification. In these design examples, the pre-calibration method is implemented to reduce the transceiver reconfiguration duration.
Figure 14. Transceiver Reconfiguration Flowchart
The following sequences describe the flow.
- Upon power up or push button reset, the DisplayPort reconfiguration module initiates the transceiver reconfiguration to sweep across all supported link rate and all lane count.
- For TX FPLL, these register offsets are reconfigured:
- 10 ’h12B (TXPLL M Counter)
- 10 ’h12C (TXPLL L Counter)
- For RX CDR, these register offsets are reconfigured:
- 10 ’h13a (RX L PFD and PD Counter)
- 10 ’h13b (RX M Counter)
- For TX FPLL, these register offsets are reconfigured:
- After reconfiguration completes, recalibration initiates per data rate.
- After calibration completes, the pre-defined calibrated registers will be stored according to the respective data rate.
- For TX FPLL, these register offsets are recalibrated:
- 10 ’h10A (PLL VCO Frequency Band 0 fix low bits)
- 10’h10B (PLL VCO Frequency Band 0 dyn)
- 10’h142 (PLL VCO Frequency Band 0 fix high bits)
- 10 ’h123 (PLL VCO Frequency Band 1 fix)
- 10’h124 (PLL VCO Frequency Band 1 dyn)
- 10’h125
- 10’h126
- For RX CDR, these register offsets are recalibrated:
- 10 ’h132 (CDR VCO Speed fix)
- 10 ’h133 (Charge Pump Vcc register)
- 10’h134 (CDR VCO Speed fix)
- 10 ’h135 (LF PFD and PD Register)
- 10 ’h136 (CDR VCO Speed fix)
- 10 ’h137 (CDR VCO Speed fix)
- 10 ’h139 (Charge Pump current PFD and PD register)
- For TX FPLL, these register offsets are recalibrated:
- Steps 1 through 3 are repeated until all supported data rates are covered.
- When the pre-calibration steps complete, the reconfiguration module is ready to start DisplayPort link training.
- Whenever the DisplayPort Intel® FPGA IP sends a new link rate request, the reconfiguration module initiates reconfiguration to the transceiver.
- The reconfiguration flow includes retrieving the calibrated register offset value that corresponds to the link rate and reconfigure it to the transceiver. No recalibration is required.
- When reconfiguration completes, the transceiver is ready to receive the link rate.
- The DisplayPort reconfiguration module continues to monitor if a new link rate request is detected. If it detects a new request, the module repeats step 5.