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1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage
2.2.1.4. Configuration 4: ADC Control Core Only
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core
5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core
5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core
5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core
5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core
5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core
5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
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5.5.2. Sample Storage Core Registers
Bit | Name | Attribute | Description | Value | Default |
---|---|---|---|---|---|
31:12 | Reserved | Read | Reserved. |
— | 0 |
11:0 | Sample | Read | The data sampled by the ADC for the corresponding slot. | Sampled data | 0 |
Bit | Name | Attribute | Description | Value | Default |
---|---|---|---|---|---|
31:28 | Reserved | Read | Reserved. | — | 0 |
27:16 | Sample | Read | The data sampled by ADC2 for the corresponding slot. | Sampled data | 0 |
15:12 | Reserved | Read | Reserved. | — | 0 |
11:0 | Sample | Read | The data sampled by ADC1 for the corresponding slot. | Sampled data | 0 |
Bit | Name | Attribute | Description | Value | Default |
---|---|---|---|---|---|
31:1 | Reserved | Read | Reserved. | — | 0 |
0 | M_EOP | Read-Write | The enable bit for the end of packet (EOP) interrupt. |
|
1 |
Bit | Name | Attribute | Description | Value | Default |
---|---|---|---|---|---|
31:1 | Reserved | Read | Reserved. | — | 0 |
0 | EOP | Read-Write (one cycle) | EOP interrupt. | This bit is automatically set by the hardware. When "1", it indicates that a packet of samples is stored and ready to be read. You can retrieve the sample value from the ADC_SAMPLE register. To clear this bit to "0" for the next interrupt, write "1". | 0 |
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