AN 738: Intel® Arria® 10 Device Design Guidelines

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ID 683555
Date 6/30/2017
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Document Table of Contents
Document Table of Contents x
1. AN 738: Intel® Arria® 10 Device Design Guidelines
1. AN 738: Intel® Arria® 10 Device Design Guidelines x
1.1. System Specification 1.2. Device Selection 1.3. Early System and Board Planning 1.4. Pin Connection Considerations for Board Design 1.5. I/O and Clock Planning 1.6. Design Entry 1.7. Design Implementation, Analysis, Optimization, and Verification 1.8. Conclusion 1.9. Document Revision History 1.10. Design Checklist 1.11. Appendix: Arria® 10 Transceiver Design Guidelines
1.1. System Specification x
1.1.1. Design Specifications 1.1.2. IP Selection 1.1.3. Qsys
1.2. Device Selection x
1.2.1. Device Family Variant and High-Speed Transceivers 1.2.2. Logic, Memory, and Multiplier Density 1.2.3. I/O Pin Count, LVDS Channels, and Package Offering 1.2.4. PLLs and Clock Routing 1.2.5. Speed Grade 1.2.6. Vertical Device Migration
1.3. Early System and Board Planning x
1.3.1. Early Power Estimation 1.3.2. Temperature Sensing for Thermal Management 1.3.3. Voltage Sensor 1.3.4. Planning for Device Configuration 1.3.5. Planning for On-Chip Debugging
1.3.4. Planning for Device Configuration x
1.3.4.1. Configuration Scheme Selection 1.3.4.2. Configuration Features 1.3.4.3. Quartus Prime Configuration Settings
1.3.4.1. Configuration Scheme Selection x
1.3.4.1.1. Serial Configuration Devices 1.3.4.1.2. Download Cables 1.3.4.1.3. Using the Parallel Flash Loader Megafunction with MAX II Devices
1.3.4.2. Configuration Features x
1.3.4.2.1. Data Compression 1.3.4.2.2. Design Security Using Configuration Bitstream Encryption 1.3.4.2.3. Remote System Upgrades 1.3.4.2.4. SEU Mitigation and CRC Error Checks
1.3.5. Planning for On-Chip Debugging x
1.3.5.1. On-Chip Debugging Tools 1.3.5.2. Planning Guidelines for Debugging Tools
1.4. Pin Connection Considerations for Board Design x
1.4.1. Device Power-Up 1.4.2. Power Pin Connections and Power Supplies 1.4.3. Configuration Pin Connections 1.4.4. Board-Related Quartus Prime Settings 1.4.5. Signal Integrity Considerations 1.4.6. Board-Level Simulation and Advanced I/O Timing Analysis
1.4.2. Power Pin Connections and Power Supplies x
1.4.2.1. Decoupling Capacitors 1.4.2.2. PLL and Transceiver Board Design Guidelines
1.4.3. Configuration Pin Connections x
1.4.3.1. DCLK and TCK Signal Integrity 1.4.3.2. JTAG Pins 1.4.3.3. MSEL Configuration Mode Pins 1.4.3.4. Other Configuration Pins
1.4.4. Board-Related Quartus Prime Settings x
1.4.4.1. Device-Wide Output Enable Pin 1.4.4.2. Unused Pins
1.4.5. Signal Integrity Considerations x
1.4.5.1. High-Speed Board Design 1.4.5.2. Voltage Reference Pins 1.4.5.3. Simultaneous Switching Noise 1.4.5.4. I/O Termination
1.5. I/O and Clock Planning x
1.5.1. Making FPGA Pin Assignments 1.5.2. Early Pin Planning and I/O Assignment Analysis 1.5.3. I/O Features and Pin Connections 1.5.4. Clock and PLL Selection 1.5.5. PLL Feature Guidelines 1.5.6. Clock Control Block 1.5.7. I/O Simultaneous Switching Noise
1.5.3. I/O Features and Pin Connections x
1.5.3.1. I/O Signaling Type 1.5.3.2. Selectable I/O Standards and Flexible I/O Banks 1.5.3.3. Memory Interfaces 1.5.3.4. Dual-Purpose and Special Pin Connections 1.5.3.5. Arria® 10 I/O Features
1.5.5. PLL Feature Guidelines x
1.5.5.1. Clock Feedback Mode 1.5.5.2. Clock Outputs
1.6. Design Entry x
1.6.1. Design Recommendations 1.6.2. Using IP Cores 1.6.3. Reconfiguration 1.6.4. Recommended HDL Coding Styles 1.6.5. Register Power-Up Levels and Control Signals 1.6.6. Planning for Hierarchical and Team-Based Design
1.6.3. Reconfiguration x
1.6.3.1. Dynamic Reconfiguration 1.6.3.2. Partial Reconfiguration
1.6.6. Planning for Hierarchical and Team-Based Design x
1.6.6.1. Planning Design Partitions 1.6.6.2. Planning in Bottom-Up and Team-Based Flows 1.6.6.3. Creating a Design Floorplan
1.7. Design Implementation, Analysis, Optimization, and Verification x
1.7.1. Selecting a Synthesis Tool 1.7.2. Device Resource Utilization Reports 1.7.3. Quartus Prime Messages 1.7.4. Timing Constraints and Analysis 1.7.5. Area and Timing Optimization 1.7.6. Preserving Performance and Reducing Compilation Time 1.7.7. Simulation 1.7.8. Formal Verification 1.7.9. Power Analysis 1.7.10. Power Optimization
1.7.4. Timing Constraints and Analysis x
1.7.4.1. Recommended Timing Optimization and Analysis Assignments
1.7.10. Power Optimization x
1.7.10.1. Device and Design Power Optimization Techniques 1.7.10.2. Quartus Prime Power Optimization Techniques
1.7.10.1. Device and Design Power Optimization Techniques x
1.7.10.1.1. Clock Power Management 1.7.10.1.2. Memory Power Reduction 1.7.10.1.3. I/O Power Guidelines
1.7.10.2. Quartus Prime Power Optimization Techniques x
1.7.10.2.1. Power Optimization Advisor
1.11. Appendix: Arria® 10 Transceiver Design Guidelines x
1.11.1. Transceiver PHY Architecture Overview 1.11.2. Transceiver Bank Architecture 1.11.3. PHY Layer Transceiver Components 1.11.4. Transceiver Phase-Locked Loops 1.11.5. Clock Generation Block (CGB) 1.11.6. Calibration 1.11.7. Transceiver Design Flow
1.11.3. PHY Layer Transceiver Components x
1.11.3.1. The GX Transceiver Channel 1.11.3.2. The GT Transceiver Channel
1.11.4. Transceiver Phase-Locked Loops x
1.11.4.1. Advanced Transmit (ATX) PLL 1.11.4.2. Fractional PLL (fPLL) 1.11.4.3. Channel PLL (CMU/CDR PLL)
1. AN 738: Intel® Arria® 10 Device Design Guidelines

1.5.1. Making FPGA Pin Assignments

Table 34.  Making FPGA Pin Assignments Checklist
Number Done? Checklist Item
1   Use the Quartus® Prime Pin Planner to make pin assignments.
2   Use Quartus® Prime Fitter messages and reports for sign-off of pin assignments.
3   Verify that the Quartus® Prime pin assignments match those in the schematic and board layout tools.

With the Quartus® Prime Pin Planner GUI, you can identify I/O banks, VREF groups, and differential pin pairings to help you through the I/O planning process. Right-click in the Pin Planner spreadsheet interface and click the Pin Finder to search for specific pins. If migration devices are selected, the Pin Migration view highlights pins that change function in the migration device when compared to the currently selected device.

You have the option of importing a Microsoft Excel spreadsheet into the Quartus® Prime software to start the I/O planning process if you normally use a spreadsheet in your design flow. You can also export a spreadsheet compatible (.csv) file containing your I/O assignments when all pins are assigned.

When you compile your design in the Quartus® Prime software, I/O Assignment Analysis in the Fitter validates that the assignments meet all the device requirements and generates messages if there are any problems.

Quartus® Prime designers can then pass the pin location information to PCB designers. Pin assignments between the Quartus® Prime software and your schematic and board layout tools must match to ensure the design works correctly on the board where it is placed, especially if changes to the pin-out must be made. The Pin Planner is integrated with certain PCB design EDA tools and can read pin location changes from these tools to check the suggested changes. When you compile your design, the Quartus® Prime software generates the .pin file. You can use this file to verify that each pin is correctly connected in the board schematics.

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