1.10. Design Checklist
Use the checklist to verify that you have followed the guidelines for each stage of your design.
| Number | Done? | N/A | Checklist Item |
| 1. | “Create detailed design specifications and a test plan if appropriate.” | ||
| 2. | “Plan clock domains, clock resources, and I/O interfaces early with a block diagram.” | ||
| 3. | “Select IP that affects system design, especially I/O interfaces.” | ||
| 4. | “If you plan to use the OpenCore Plus tethered mode for IP, ensure that your board design supports this mode of operation.” | ||
| 5. | “Take advantage of Qsys for system and processor designs.” | ||
| 6. | “Select a device based on transceivers, I/O pin count, LVDS channels, package offering, logic/memory/multiplier density, PLLs, clock routing, and speed grade.” | ||
| 7. | “Reserve device resources for future development and debugging.” | ||
| 8. | “Consider vertical device migration availability and requirements.” | ||
| 9. | “Estimate power consumption with the Early Power Estimator (EPE) spreadsheet to plan the cooling solution and power supplies before the logic design is complete.” | ||
| 10. | “Set up the temperature sensing diode in your design to measure the device junction temperature for thermal management.” | ||
| 11. | “Select a configuration scheme to plan companion devices and board connections.” | ||
| 12. | “If you want to use the AS configuration mode with large device densities, confirm there is a configuration device available that is large enough for your target FPGA density.” | ||
| 13. | “If you want to use a flash device with the parallel flash loader, check the list of supported devices.” | ||
| 14. | “Ensure your configuration scheme and board support the following required features: data decompression, design security, remote upgrades, single event updates (SEU) mitigation.” | ||
| 15. | “Plan the board design to support optional configuration pins CLKUSR and INIT_DONE, as required.” | ||
| 16. | “Plan board design to use the Auto-restart after configuration error option.” | ||
| 17. | “Take advantage of on-chip debugging features to analyze internal signals and perform advanced debugging techniques. The ARM DS-5 <keyword keyref="companyname-tm"/> Edition offers you a variety of debugging features for SoC designs.” | ||
| 18. | “Select on-chip debugging scheme(s) early to plan memory and logic requirements, I/O pin connections, and board connections.” | ||
| 19. | “If you want to use Signal Probe incremental routing, the SignalTap II Embedded Logic Analyzer, Logic Analyzer Interface, In-System Memory Content Editor, In-System Sources and Probes, or Virtual JTAG megafunction, plan your system and board with JTAG connections that are available for debugging.” | ||
| 20. | “Plan for the small amount of additional logic resources used to implement the JTAG hub logic for JTAG debugging features.” | ||
| 21. | “For debugging with the SignalTap II Embedded Logic Analyzer, reserve device memory resources to capture data during system operation.” | ||
| 22. | “Reserve I/O pins for debugging with Signal Probe or the Logic Analyzer Interface so you do not have to change the design or board to accommodate debugging signals later.” | ||
| 23. | “Ensure the board supports a debugging mode where debugging signals do not affect system operation.” | ||
| 24. | “Incorporate a pin header or mictor connector as required for an external logic analyzer or mixed signal oscilloscope.” | ||
| 25. | “To use debug tools incrementally and reduce compilation time, ensure incremental compilation is on so you do not have to recompile the design to modify the debug tool.” | ||
| 26. | “To use the Virtual JTAG megafunction for custom debugging applications, instantiate it in the HDL code as part of the design process.” | ||
| 27. | “To use the In-System Sources and Probes feature, instantiate the megafunction in the HDL code.” | ||
| 28. | “To use the In-System Memory Content Editor for RAM or ROM blocks or the LPM_CONSTANT megafunction, turn on the Allow In-System Memory Content Editor to capture and update content independently of the system clock option for the memory block in the IP catalog.” | ||
| 29. | “Design board for power-up: Arria® 10 output buffers are tri-stated until the device is configured and configuration pins drive out.” | ||
| 30. | “Design voltage power supply ramps to be monotonic.” | ||
| 31. | “Set POR time to ensure power supplies are stable.” | ||
| 32. | “Design power sequencing and voltage regulators for best device reliability. Connect the GND between boards before connecting the power supplies.” | ||
| 33. | “Connect all power pins correctly as specified in the Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.” | ||
| 34. | “Connect VCCIO pins and VREF pins to support each bank’s I/O standards.” | ||
| 35. | “Explore unique requirements for FPGA power pins or other power pins on your board, and determine which devices on your board can share a power rail.” | ||
| 36. | “Follow the suggested power supply sharing and isolation guidance, and the specific guidelines for each pin in the Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.” | ||
| 37. | “Use the PDN tool to plan your power distribution netlist and decoupling capacitors.” | ||
| 38. | “Connect all PLL power pins to reduce noise even if the design does not use all the PLLs. For pin voltage requirements, refer to the Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.” | ||
| 39. | “Power supply nets should be provided by an isolated power plane, a power plane cut out, or thick trace of at least 20 mils.” | ||
| 40. | “Check that all configuration pin connections and pull-up/pull-down resistors are set correctly for your configuration scheme(s).” | ||
| 41. | “Design configuration DCLK and TCK pins to be noise-free.” | ||
| 42. | “Connect JTAG pins to a stable voltage level if not in use.” | ||
| 43. | “Connect JTAG pins correctly to the download cable header. Ensure the pin order is not reversed.” | ||
| 44. | “To disable the JTAG state machine during power-up, pull the TCK pin low through a 1-kW resistor to ensure that an unexpected rising edge does not occur on TCK.” | ||
| 45. | “Pull TMS and TDI high through a 1-k to 10-kW resistor.” | ||
| 46. | “Connect TRST directly to VCCPGM (Connecting the pin low disables the JTAG circuitry).” | ||
| 47. | “Because the download cable interfaces with the JTAG pins of your device, ensure the download cable and JTAG pin voltages are compatible.” | ||
| 48. | “Buffer JTAG signals per the recommendations, especially for connectors or if the cable drives more than three devices.” | ||
| 49. | “If your device is in a configuration chain, ensure all devices in the chain are connected properly.” | ||
| 50. | “Connect the MSEL pins to a select configuration scheme; do not leave them floating. For flexibility to change between configuration modes during testing or debugging, set up the board to connect each pin to either VCCPGM or GND without pull-up or pull-down resistors.” | ||
| 51. | “Connect nIO_PULLUP directly to GND.” | ||
| 52. | “Hold the nCE (chip enable) pin low during configuration, initialization, and user mode.” | ||
| 53. | “Turn on the device-wide output enable option, if required.” | ||
| 54. | “Specify the reserved state for unused I/O pins.” | ||
| 55. | “Carefully check the pin connections in the Quartus Prime software-generated .pin. Do not connect RESERVED pins.” | ||
| 56. | “Design VREF pins to be noise-free.” | ||
| 57. | “Break out large bus signals on board layers close to the device to reduce cross talk.” | ||
| 58. | “Route traces orthogonally if two signal layers are next to each other, if possible. Use a separation of 2 to 3 times the trace width.” | ||
| 59. | “Check I/O termination and impedance matching for chosen I/O standards, especially for voltage-referenced standards.” | ||
| 60. | “Perform board-level simulation using IBIS models (when available).” | ||
| 61. | “Configure board trace models for Quartus Prime advanced I/O timing analysis.” | ||
| 62. | “Use the Quartus Prime Pin Planner to make pin assignments.” | ||
| 63. | “Use Quartus Prime Fitter messages and reports for sign-off of pin assignments.” | ||
| 64. | “Verify that the Quartus Prime pin assignments match those in the schematic and board layout tools.” | ||
| 65. | “Use the Create Top-Level Design File command with I/O Assignment Analysis to check the I/O assignments before the design is complete.” | ||
| 66. | “Plan the I/O signaling type based on the system requirements.” | ||
| 67. | “Allow the software to assign locations for the negative pin in differential pin pairs.” | ||
| 68. | “Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, DPA, and SERDES circuitries.” | ||
| 69. | “Ensure that the appropriate I/O standard support is supported in the targeted I/O bank.” | ||
| 70. | “Place I/O pins that share voltage levels in the same I/O bank.” | ||
| 71. | “Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.” | ||
| 72. | “Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.” | ||
| 73. | “Check the I/O bank support for LVDS and transceiver features.” | ||
| 74. | “Use the Arria® 10 EMIF IP megafunction (or IP core) for each memory interface, and follow connection guidelines/restrictions in the appropriate documentation.” | ||
| 75. | “Use dedicated DQ/DQS pins and DQ groups for memory interfaces.” | ||
| 76. | “Make dual-purpose pin settings and check for any restrictions when using these pins as regular I/O.” | ||
| 77. | “Check available device I/O features that can help I/O interfaces: current strength, slew rate, I/O delays, open-drain, bus hold, programmable pull-up resistors, PCI clamping diodes, programmable pre-emphasis, and VOD.” | ||
| 78. | “Consider OCT features to save board space.” | ||
| 79. | “Verify that the required termination scheme is supported for all pin locations.” | ||
| 80. | “Choose the appropriate mode of DPA, non-DPA, or soft-CDR for high-speed LVDS interfaces.” | ||
| 81. | “Use the correct dedicated clock pins and routing signals for clock and global control signals.” | ||
| 82. | “Use the device fractional PLLs for clock management.” | ||
| 83. | “Analyze input and output routing connections for each PLL and clock pin. Ensure PLL inputs come from the dedicated clock pins or from another PLL.” | ||
| 84. | “Enable PLL features and check settings in the parameter editor.” | ||
| 85. | “Ensure you select the correct PLL feedback compensation mode.” | ||
| 86. | “Check that the PLL offers the required number of clock outputs and use dedicated clock output pins.” | ||
| 87. | “Use the clock control block for clock selection and power-down.” | ||
| 88. | “Analyze the design for possible SSN problems.” | ||
| 89. | “Reduce the number of pins that switch the voltage level at exactly the same time whenever possible.” | ||
| 90. | “Use differential I/O standards and lower-voltage standards for high-switching I/Os.” | ||
| 91. | “Use lower drive strengths for high-switching I/Os. The default drive strength setting might be higher than your design requires.” | ||
| 92. | “Reduce the number of simultaneously switching output pins within each bank. Spread output pins across multiple banks if possible.” | ||
| 93. | “Spread switching I/Os evenly throughout the bank to reduce the number of aggressors in a given area to reduce SSN (when bank usage is substantially below 100%).” | ||
| 94. | “Separate simultaneously switching pins from input pins that are susceptible to SSN.” | ||
| 95. | “Place important clock and asynchronous control signals near ground signals and away from large switching buses.” | ||
| 96. | “Avoid using I/O pins one or two pins away from PLL power supply pins for high-switching or high-drive strength pins.” | ||
| 97. | “Use staggered output delays to shift the output signals through time, or use adjustable slew rate settings.” | ||
| 98. | “Use synchronous design practices. Pay attention to clock signals.” | ||
| 99. | “Use the Quartus II Design Assistant to check design reliability.” | ||
| 99. | “Use megafunctions with the parameter editor.” | ||
| 100. | “Follow recommended coding styles, especially for inferring device dedicated logic such as memory and DSP blocks.” | ||
| 101. | “Enable the chip-wide reset to clear all registers if required.” | ||
| 102. | “Consider resources available for register power-up and control signals. Do not apply both reset and preset signals to a register.” | ||
| 103. | “Follow recommendations to set up your source code and partition your design for incremental compilation; plan early in the design flow.” | ||
| 104. | “Perform timing budgeting and resource balancing between partitions to achieve best results, especially in team-based flows.” | ||
| 105. | “Create a design floorplan for incremental compilation partitions, if required for your design flow.” | ||
| 106. | “Specify your third-party synthesis tool and use the correct supported version.” | ||
| 107. | “Review resource utilization reports after compilation.” | ||
| 108. | “Review all Quartus Prime messages, especially warning or error messages.” | ||
| 109. | “Ensure timing constraints are complete and accurate, including all clock signals and I/O delays.” | ||
| 110. | “Review the TimeQuest Timing Analyzer reports after compilation to ensure there are no timing violations.” | ||
| 111. | “Ensure that the input I/O times are not violated when data is provided to the Arria® 10 device.” | ||
| 112. | “Turn on Optimize multi-corner timing on the Fitter Settings page in the Settings dialog box.” | ||
| 113. | “Use create_clock and create_generated_clock to specify the frequencies and relationships for all clocks in your design.” | ||
| 114. | “Use set_input_delay and set_output_delay to specify the external device or board timing parameters.” | ||
| 115. | “Use derive_pll_clocks to create generated clocks for all PLL outputs, according to the settings in the PLL megafunctions. Specify multicycle relationships for LVDS transmitters or receiver deserialization factors.” | ||
| 116. | “Use derive_clock_uncertainty to automatically apply inter-clock, intra-clock, and I/O interface uncertainties.” | ||
| 117. | “Use check_timing to generate a report on any problem with the design or applied constraints, including missing constraints.” | ||
| 118. | “Perform Early Timing Estimation if you want timing estimates before running a full compilation.” | ||
| 119. | “Use Quartus Prime optimization features to achieve timing closure or improve the resource utilization.” | ||
| 120. | “Use the Timing and Area Optimization Advisors to suggest optimization settings.” | ||
| 121. | “Use incremental compilation to preserve performance for unchanged blocks in your design and to reduce compilation times.” | ||
| 122. | “Ensure parallel compilation is enabled if you have multiple processors available for compilation.” | ||
| 123. | “Use the Compilation Time Advisor to suggest settings that reduce compilation time.” | ||
| 124. | “Specify your third-party simulation tool, and use the correct supported version and simulation models.” | ||
| 125. | “Specify your third-party formal verification tool and use the correct supported version.” | ||
| 126. | “If you use formal verification, check for support and design limitations.” | ||
| 127. | “After compilation, analyze power consumption and heat dissipation in the Power Analyzer.” | ||
| 128. | “Provide accurate typical signal activities, preferably with a gate-level simulation .vcd, to get accurate power analysis results.” | ||
| 129. | “Specify the correct operating conditions for power analysis.” | ||
| 130. | “Use recommended design techniques and Quartus Prime options to optimize your design for power consumption, if required.” | ||
| 131. | “Use the Power Optimization Advisor to suggest optimization settings.” |