Visible to Intel only — GUID: wxu1487184665374
Ixiasoft
Visible to Intel only — GUID: wxu1487184665374
Ixiasoft
1.3.4.1. Configuration Scheme Selection
- Fast passive parallel (FPP)—A controller supplies the configuration data in a parallel manner to the Arria® 10 FPGA. FPP is supported in an 8-bit (FPP ×8), 16-bit (FPP ×16) or 32-bit data width (FPP ×32).
- Active serial (AS)—The Arria® 10 FPGA controls the configuration process and gets the configuration data from a qual-serial configuration (EPCQ-L ) device. AS is supported in 1-bit (AS ×1) or 4-bit data width (AS ×4).
- Passive serial (PS)—An external host supplies the configuration data serially to the Arria® 10 FPGA.
- Joint Test Action Group (JTAG)—Configured using the IEEE Standard 1149.1 interface with a download cable, or using MAX (MAX II, MAX V, MAX 10) devices, or microprocessor with flash memory.
You can enable any specific configuration scheme by driving the Arria® 10 device MSEL pins to specific values on the board.
Number | Done? | Checklist Item |
---|---|---|
1 | Select a configuration scheme to plan companion devices and board connections. |
All configuration schemes use a configuration device, a download cable, or an external controller (for example, MAX® ( MAX® II, MAX® V, MAX® 10) devices or microprocessor).