AN 738: Intel® Arria® 10 Device Design Guidelines

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Date 6/30/2017
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Document Table of Contents
Document Table of Contents x
1. AN 738: Intel® Arria® 10 Device Design Guidelines
1. AN 738: Intel® Arria® 10 Device Design Guidelines x
1.1. System Specification 1.2. Device Selection 1.3. Early System and Board Planning 1.4. Pin Connection Considerations for Board Design 1.5. I/O and Clock Planning 1.6. Design Entry 1.7. Design Implementation, Analysis, Optimization, and Verification 1.8. Conclusion 1.9. Document Revision History 1.10. Design Checklist 1.11. Appendix: Arria® 10 Transceiver Design Guidelines
1.1. System Specification x
1.1.1. Design Specifications 1.1.2. IP Selection 1.1.3. Qsys
1.2. Device Selection x
1.2.1. Device Family Variant and High-Speed Transceivers 1.2.2. Logic, Memory, and Multiplier Density 1.2.3. I/O Pin Count, LVDS Channels, and Package Offering 1.2.4. PLLs and Clock Routing 1.2.5. Speed Grade 1.2.6. Vertical Device Migration
1.3. Early System and Board Planning x
1.3.1. Early Power Estimation 1.3.2. Temperature Sensing for Thermal Management 1.3.3. Voltage Sensor 1.3.4. Planning for Device Configuration 1.3.5. Planning for On-Chip Debugging
1.3.4. Planning for Device Configuration x
1.3.4.1. Configuration Scheme Selection 1.3.4.2. Configuration Features 1.3.4.3. Quartus Prime Configuration Settings
1.3.4.1. Configuration Scheme Selection x
1.3.4.1.1. Serial Configuration Devices 1.3.4.1.2. Download Cables 1.3.4.1.3. Using the Parallel Flash Loader Megafunction with MAX II Devices
1.3.4.2. Configuration Features x
1.3.4.2.1. Data Compression 1.3.4.2.2. Design Security Using Configuration Bitstream Encryption 1.3.4.2.3. Remote System Upgrades 1.3.4.2.4. SEU Mitigation and CRC Error Checks
1.3.5. Planning for On-Chip Debugging x
1.3.5.1. On-Chip Debugging Tools 1.3.5.2. Planning Guidelines for Debugging Tools
1.4. Pin Connection Considerations for Board Design x
1.4.1. Device Power-Up 1.4.2. Power Pin Connections and Power Supplies 1.4.3. Configuration Pin Connections 1.4.4. Board-Related Quartus Prime Settings 1.4.5. Signal Integrity Considerations 1.4.6. Board-Level Simulation and Advanced I/O Timing Analysis
1.4.2. Power Pin Connections and Power Supplies x
1.4.2.1. Decoupling Capacitors 1.4.2.2. PLL and Transceiver Board Design Guidelines
1.4.3. Configuration Pin Connections x
1.4.3.1. DCLK and TCK Signal Integrity 1.4.3.2. JTAG Pins 1.4.3.3. MSEL Configuration Mode Pins 1.4.3.4. Other Configuration Pins
1.4.4. Board-Related Quartus Prime Settings x
1.4.4.1. Device-Wide Output Enable Pin 1.4.4.2. Unused Pins
1.4.5. Signal Integrity Considerations x
1.4.5.1. High-Speed Board Design 1.4.5.2. Voltage Reference Pins 1.4.5.3. Simultaneous Switching Noise 1.4.5.4. I/O Termination
1.5. I/O and Clock Planning x
1.5.1. Making FPGA Pin Assignments 1.5.2. Early Pin Planning and I/O Assignment Analysis 1.5.3. I/O Features and Pin Connections 1.5.4. Clock and PLL Selection 1.5.5. PLL Feature Guidelines 1.5.6. Clock Control Block 1.5.7. I/O Simultaneous Switching Noise
1.5.3. I/O Features and Pin Connections x
1.5.3.1. I/O Signaling Type 1.5.3.2. Selectable I/O Standards and Flexible I/O Banks 1.5.3.3. Memory Interfaces 1.5.3.4. Dual-Purpose and Special Pin Connections 1.5.3.5. Arria® 10 I/O Features
1.5.5. PLL Feature Guidelines x
1.5.5.1. Clock Feedback Mode 1.5.5.2. Clock Outputs
1.6. Design Entry x
1.6.1. Design Recommendations 1.6.2. Using IP Cores 1.6.3. Reconfiguration 1.6.4. Recommended HDL Coding Styles 1.6.5. Register Power-Up Levels and Control Signals 1.6.6. Planning for Hierarchical and Team-Based Design
1.6.3. Reconfiguration x
1.6.3.1. Dynamic Reconfiguration 1.6.3.2. Partial Reconfiguration
1.6.6. Planning for Hierarchical and Team-Based Design x
1.6.6.1. Planning Design Partitions 1.6.6.2. Planning in Bottom-Up and Team-Based Flows 1.6.6.3. Creating a Design Floorplan
1.7. Design Implementation, Analysis, Optimization, and Verification x
1.7.1. Selecting a Synthesis Tool 1.7.2. Device Resource Utilization Reports 1.7.3. Quartus Prime Messages 1.7.4. Timing Constraints and Analysis 1.7.5. Area and Timing Optimization 1.7.6. Preserving Performance and Reducing Compilation Time 1.7.7. Simulation 1.7.8. Formal Verification 1.7.9. Power Analysis 1.7.10. Power Optimization
1.7.4. Timing Constraints and Analysis x
1.7.4.1. Recommended Timing Optimization and Analysis Assignments
1.7.10. Power Optimization x
1.7.10.1. Device and Design Power Optimization Techniques 1.7.10.2. Quartus Prime Power Optimization Techniques
1.7.10.1. Device and Design Power Optimization Techniques x
1.7.10.1.1. Clock Power Management 1.7.10.1.2. Memory Power Reduction 1.7.10.1.3. I/O Power Guidelines
1.7.10.2. Quartus Prime Power Optimization Techniques x
1.7.10.2.1. Power Optimization Advisor
1.11. Appendix: Arria® 10 Transceiver Design Guidelines x
1.11.1. Transceiver PHY Architecture Overview 1.11.2. Transceiver Bank Architecture 1.11.3. PHY Layer Transceiver Components 1.11.4. Transceiver Phase-Locked Loops 1.11.5. Clock Generation Block (CGB) 1.11.6. Calibration 1.11.7. Transceiver Design Flow
1.11.3. PHY Layer Transceiver Components x
1.11.3.1. The GX Transceiver Channel 1.11.3.2. The GT Transceiver Channel
1.11.4. Transceiver Phase-Locked Loops x
1.11.4.1. Advanced Transmit (ATX) PLL 1.11.4.2. Fractional PLL (fPLL) 1.11.4.3. Channel PLL (CMU/CDR PLL)
1. AN 738: Intel® Arria® 10 Device Design Guidelines

1.5.3.5. Arria® 10 I/O Features

The Arria® 10 bi-directional I/O element (IOE) features support rapid system integration while simultaneously providing the high bandwidth required to maximize internal logic capabilities and system-level performance. Advanced features for device interfaces assist in high-speed data transfer into and out of the device and reduce the complexity and cost of the PCB.
Table 40.   Arria® 10 I/O Features
Feature Usage Guidelines and More Information
MultiVolt I/O Interface Allows all packages to interface with systems of different supply voltages. VCCIO pins can be connected to a 1.2-, 1.25-, 1.35-, 1.5-, 1.8-, 2.5-, or 3.0-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply. VCCPD power pins must be connected to a 2.5- or 3.0-V power supply. Refer to the previous sections and the I/O and High Speed I/O in Arria® 10 Devices chapter of the Arria® 10 Core Fabric and General Purpose I/O Handbook for a summary of MultiVolt I/O support and a list of the supported I/O standards and the typical values for input and output VCCIO, VCCPD, VREF, and board termination voltage (VTT). Intel® recommends that you use an external clamp diode on the all I/O pins when the input signal is 3.0 V.
Programmable Output Current Strength Programmable current-strength control is available for certain I/O standards. You can mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane. A higher current strength increases I/O performance, but also increases noise on the interface, so you can use current strength control to manage noise. Ensure that the output buffer current strength is sufficiently high, but does not cause excessive overshoot or undershoot that violates voltage threshold parameters for the I/O standard. Intel® recommends performing an IBIS or SPICE simulations to determine the right current strength setting for your specific application. For a list of standards and settings, refer to the I/O and High Speed I/O in Arria® 10 Devices chapter of the Arria® 10 Core Fabric and General Purpose I/O Handbook.
Programmable Slew Rate Control Configure each pin for low-noise or high-speed performance. A faster slew rate provides high speed transitions. You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. A slow slew rate can help reduce system noise, but adds a nominal delay to rising and falling edges. You can use the slew rate to reduce SSN. Confirm that your interface meets its performance requirements if you use slower slew rates. Intel® recommends performing IBIS or SPICE simulations to determine the right slew rate setting for your specific application.
Programmable IOE Delay Programmable delay chains can ensure zero hold times, minimize setup times, or increase clock-to-output times. You can use delays as deskewing circuitry to ensure that all bits of a bus have the same delay going into or out of the device. This feature helps read and time margins because it minimizes the uncertainties between signals in the bus. For delay specifications, refer to the Arria® 10 Device Datasheet.
Programmable Output Buffer Delay Delay chains in the single-ended output buffer can independently control the rising and falling edge delays of the output buffer. You can use delays to adjust the output buffer duty cycle, compensate channel-to-channel skew, reduce SSO noise by deliberately introducing channel-to-channel skew, and improve high-speed memory-interface timing margins.
Open-Drain Output When configured as an open-drain, the logic value of the output is either high-Z or 0. Used in system-level control signals that can be asserted by multiple devices in the system. Typically, an external pull-up resistor is required to provide logic high.
Bus Hold Weakly holds the signal on an I/O pin at its last driven state until the next input signal is present, using a resistor with a nominal resistance (RBH) of approximately 7 kΩ . With this feature, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated. The circuitry also pulls non-driven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. If the bus-hold feature is enabled, you cannot use the programmable pull-up option. Disable the bus-hold feature if the I/O pin is configured for differential signals. For the specific sustaining current driven through this resistor and the overdrive current used to identify the next driven input and level for each VCCIO voltage, refer to the Arria® 10 Device Datasheet.
Programmable Pull-Up Resistor Pull-up resistor (typically 25 kΩ) weakly holds the I/O to the VCCIO level when in user mode. Can be used with the open-drain output to eliminate the requirement for an external pull-up resistor. If the programmable pull-up option is enabled, you cannot use the bus-hold feature.
On-Chip Termination (OCT) Driver-impedance matching provides the I/O driver with controlled output impedance that closely matches the impedance of the transmission line to significantly reduce reflections. OCT maintains signal quality, saves board space, and reduces external component costs. Support for on-chip series (RS) with or without calibration, parallel (RT) with calibration, and dynamic series and parallel termination for single-ended I/O standards and on-chip differential termination (RD) for differential LVDS I/O standards. OCT RS and RT are supported in the same I/O bank for different I/O standards if they use the same VCCIO supply voltage. Each I/O in an I/O bank can be independently configured to support OCT RS, programmable current strength, or OCT RT. You cannot configure both OCT RS and programmable current strength or slew rate control for the same I/O buffer. Differential OCT RD is available in all I/O pins. For details about the support and implementation of this feature, refer to the I/O and High Speed I/O in Arria® 10 Devices chapter of the Arria® 10 Core Fabric and General Purpose I/O Handbook.
Programmable Pre-Emphasis Increases the amplitude of the high frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line. Refer to the I/O and High Speed I/O in Arria® 10 Devices chapter of the Arria® 10 Core Fabric and General Purpose I/O Handbook.
Programmable Differential Output Voltage Allows you to adjust output eye height to optimize trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end while a smaller VOD swing reduces power consumption. Refer to the I/O and High Speed I/O in Arria® 10 Devices chapter of the Arria® 10 Core Fabric and General Purpose I/O Handbook.
Dedicated Differential I/O SERDES Circuitry with DPA and Soft-CDR Support All the I/Os in Arria® 10 GX devices and E devices have built-in SERDES circuitry that supports high-speed LVDS interfaces at data rates of up to 1600 Mbps. DPA circuitry automatically chooses the best phase to compensate the skew between the source synchronous clock and received serial data. The soft-CDR mode provides the opportunity for synchronous/asynchronous applications for chip-to-chip and short reach board-to-board applications for SGMII protocols. If you want to use DPA, enable the feature in the parameter editor. DPA usage adds some constraints on the placement of high-speed differential channels. Refer to the feature description and placement guidelines in the I/O and High Speed I/O in Arria® 10 Devices chapter of the Arria® 10 Core Fabric and General Purpose I/O Handbook.

Refer to the Stratix V I/O banks figure that shows the location of each I/O bank and what each bank supports. The figures describing the number of I/Os in each bank provide bank information specific to each device density. Refer to the section describing I/O bank restrictions for information about which I/O standards can be combined in each bank, and the section describing I/O placement guidelines for details about LVDS restrictions.

Consider the following checklist items and refer to the appropriate documentation in Table 3 for detailed guidelines:

Table 41.   Arria® 10 I/O Features Checklist
Number Done? Checklist Item
1   Check available device I/O features that can help I/O interfaces: current strength, slew rate, I/O delays, open-drain, bus hold, programmable pull-up resistors, PCI clamping diodes, programmable pre-emphasis, and VOD.
2   Consider on-chip termination (OCT) features to save board space.
3   Verify that the required termination scheme is supported for all pin locations.
4   Choose the appropriate mode of DPA, non-DPA, or soft-CDR for high-speed LVDS interfaces.
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