Visible to Intel only — GUID: uvl1614198342853
Ixiasoft
Visible to Intel only — GUID: uvl1614198342853
Ixiasoft
2. Quick Start Guide
Using the Quartus® Prime Pro Edition software, you can generate a programmed I/O (PIO) design example for the Intel® FPGA R-Tile Avalon® -ST Hard IP for PCI Express* IP core. The generated design example reflects the parameters that you specify. The PIO example transfers data from a host processor to a target device. It is appropriate for low-bandwidth applications. This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime Pro Edition software. You can download a compiled version of this PIO design example to the Agilex™ 7 I-Series ES FPGA Development Board for evaluation. To download to custom hardware, update the Quartus® Prime Settings File (.qsf) with the correct pin assignments .