R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683544
Date 11/05/2024
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Document Table of Contents
Document Table of Contents x
1. Functional Descriptions of the Design Examples 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. Functional Descriptions of the Design Examples x
1.1. Glossary of Terms 1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express x
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.2.3. Functional Description for the Performance Design Example 1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode 1.2.5. Hardware and Software Requirements
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example x
1.2.1.1. Credit Initialization Sequence
1.2.1.1. Credit Initialization Sequence x
1.2.1.1.1. Credit Value Initialization and Return 1.2.1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example
2.2. Generating the Design Example x
2.2.1. Generating the Design Example with R-Tile Configured in PIPE Mode 2.2.2. Generating the Performance Design Example for TL Bypass Mode
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Siemens EDA QuestaSim* Simulator 2.3.1.2. VCS* Simulator 2.3.1.3. VCS* MX Simulator 2.3.1.4. Xcelium* Simulator
2.3.2. Testbench x
2.3.2.1. Testbench Modules 2.3.2.2. Test Driver Module 2.3.2.3. PIO Design Example Testbench 2.3.2.4. SR-IOV Design Example Testbench
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
2.7. Running the Design Example x
2.7.1. Running the PIO Design Example 2.7.2. Running the SR-IOV Design Example 2.7.3. Running the Performance Design Example (Endpoint) 2.7.4. Running the Performance Design Example for TL Bypass Mode
1. Functional Descriptions of the Design Examples
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example

The SR-IOV design example performs memory transfers from a host processor to a target device. It only supports two Physical Functions (PFs) and 32 Virtual Functions (VFs) per PF. Note that this design example does not support back-to-back transactions from the host processor since the design is intended to showcase single-dword transactions. In addition, the addresses for all the transactions must be dword-aligned.

This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to an Agilex™ 7 I-Series FPGA Development Kit.

Table 7.  Configurations Supported by the SR-IOV Design ExampleSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Link Speed Data Width (Bits) Design Example Support Simulators Support
Endpoint x16 Gen 5 1024 (4 x 256) SCTH VCS* , VCS* MX, Siemens* EDA QuestaSim* , Xcelium* 4
N/A N/A N/A N/A
N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A
x8 N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A
x4 N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A
Root Port N/A N/A N/A N/A N/A
TL Bypass N/A N/A N/A N/A N/A
PIPE-D N/A N/A N/A N/A N/A
Note: This design example supports payload sizes of up to 388 Bytes only.
This design example includes the following components:
  • The generated R-Tile Avalon Streaming (Avalon-ST) IP Endpoint variant (DUT) with the parameters you specified. This component drives the received TLP data to the SR-IOV application.
  • The SR-IOV Application (APPS) component, which performs the necessary translation between the PCI Express TLPs and Avalon-ST writes and reads to the on-chip memory. For the SR-IOV APPS component, a memory read TLP generates a Completion with data.
  • A Reset Release IP.

The simulation testbench instantiates the SR-IOV design example and a Root Port BFM to interface with the target Endpoint.

Figure 8. Block Diagram for the Platform Designer SR-IOV Design Example Simulation Testbench

The test program writes to and reads back data from the same location in the on-chip memory across 2 PFs and 32 VFs per PF. It compares the data read to the expected result. The test reports, "Simulation stopped due to successful completion" if no errors occur.

Figure 9.  Platform Designer System Contents for the R-Tile Avalon-ST IP with SR-IOV for PCI Express 1x16 Design Example
4 Xcelium* simulator support is only available in devices with the following OPN numbers: AGIx027R29AxxxxR3, AGIx027R29AxxxxR2, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1. For more details on OPN decoding, refer to the Agilex™ 7 FPGAs and SoCs Device Overview.
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