R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683544
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Functional Descriptions of the Design Examples 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. Functional Descriptions of the Design Examples x
1.1. Glossary of Terms 1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express x
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.2.3. Functional Description for the Performance Design Example 1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode 1.2.5. Hardware and Software Requirements
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example x
1.2.1.1. Credit Initialization Sequence
1.2.1.1. Credit Initialization Sequence x
1.2.1.1.1. Credit Value Initialization and Return 1.2.1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example
2.2. Generating the Design Example x
2.2.1. Generating the Design Example with R-Tile Configured in PIPE Mode 2.2.2. Generating the Performance Design Example for TL Bypass Mode
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Siemens EDA QuestaSim* Simulator 2.3.1.2. VCS* Simulator 2.3.1.3. VCS* MX Simulator 2.3.1.4. Xcelium* Simulator
2.3.2. Testbench x
2.3.2.1. Testbench Modules 2.3.2.2. Test Driver Module 2.3.2.3. PIO Design Example Testbench 2.3.2.4. SR-IOV Design Example Testbench
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
2.7. Running the Design Example x
2.7.1. Running the PIO Design Example 2.7.2. Running the SR-IOV Design Example 2.7.3. Running the Performance Design Example (Endpoint) 2.7.4. Running the Performance Design Example for TL Bypass Mode
1. Functional Descriptions of the Design Examples
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.4. Root Port BFM

The Root Port BFM provides a Verilog HDL task‑based interface to request transactions to issue on the PCI Express link. The Root Port BFM also handles requests received from the PCI Express link. The following figure shows the major modules in the Root Port BFM.

Figure 31. Root Port BFM

These modules implement the following functionality:

  • BFM Log Interface, altpcietb_g3bfm_log.v and altpcietb_bfm_rp_gen5_x16.sv: The BFM Log Interface provides routines for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulations on errors.
  • BFM Read/Write Request Functions, altpcietb_bfm_rp_gen5_x16.sv: These functions provide the basic BFM calls for PCI Express read and write requests.
  • BFM Configuration Functions, altpcietb_g3bfm_configure.v: These functions provide the BFM calls to request a configuration of the PCI Express link and the Endpoint Configuration Space registers.
  • BFM shared memory, altpcietb_g3bfm_shmem.v: This module provides the Root Port BFM shared memory. It implements the following functionality:
    • Provides data for TX write operations
    • Provides data for RX read operations
    • Receives data for RX write operations
    • Receives data for received completions
  • BFM Request Interface, altpcietb_g3bfm_req_intf.v: This interface provides the low-level interface between the altpcietb_g3bfm_rdwr and altpcietb_g3bfm_configure procedures or functions and the Root Port RTL Model. This interface stores a write-protected data structure containing the sizes and values programmed in the BAR registers of the Endpoint. It also stores other critical data used for internal BFM management.
  • altpcietb_g3bfm_rdwr.v: This module contains the low-level read and write tasks.
  • Avalon‑ST Interfaces, altpcietb_g3bfm_vc_intf_ast_common.v: These interface modules handle the Root Port interface model. They take requests from the BFM request interface and generate the required PCI Express transactions. They handle completions received from the PCI Express link and notify the BFM request interface when requests are complete. Additionally, they handle any requests received from the PCI Express link, and store or fetch data from the shared memory before generating the required completions.

In the PIO design example, the apps_type_hwtcl parameter is set to 3. The tests run under this parameter value are defined in ebfm_cfg_rp_ep_rootport, find_mem_bar, and downstream_loop.

The function ebfm_cfg_rp_ep_rootport is described in altpcietb_g3bfm_configure.v. This function performs the steps necessary to configure the root port and the endpoint on the link. It includes:
  • Root port memory allocation
  • Root port configuration space (base limit, bus number, etc.)
  • Endpoint configuration (BAR, Bus Master enable, max payload size, etc.)

The functions find_mem_bar and downstream_loop in altpcietb_bfm_rp_gen5_x16.sv return the BAR implemented and perform the memory Write and Read accesses to the BAR, respectively.


Section Content
BFM Memory Map
Configuration Space Bus and Device Numbering
Configuration of Root Port and Endpoint
Issuing Read and Write Transactions to the Application Layer
BFM Procedures and Functions

Level Two Title