R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683544
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Functional Descriptions of the Design Examples 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. Functional Descriptions of the Design Examples x
1.1. Glossary of Terms 1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express x
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.2.3. Functional Description for the Performance Design Example 1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode 1.2.5. Hardware and Software Requirements
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example x
1.2.1.1. Credit Initialization Sequence
1.2.1.1. Credit Initialization Sequence x
1.2.1.1.1. Credit Value Initialization and Return 1.2.1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example
2.2. Generating the Design Example x
2.2.1. Generating the Design Example with R-Tile Configured in PIPE Mode 2.2.2. Generating the Performance Design Example for TL Bypass Mode
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Siemens EDA QuestaSim* Simulator 2.3.1.2. VCS* Simulator 2.3.1.3. VCS* MX Simulator 2.3.1.4. Xcelium* Simulator
2.3.2. Testbench x
2.3.2.1. Testbench Modules 2.3.2.2. Test Driver Module 2.3.2.3. PIO Design Example Testbench 2.3.2.4. SR-IOV Design Example Testbench
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
2.7. Running the Design Example x
2.7.1. Running the PIO Design Example 2.7.2. Running the SR-IOV Design Example 2.7.3. Running the Performance Design Example (Endpoint) 2.7.4. Running the Performance Design Example for TL Bypass Mode
1. Functional Descriptions of the Design Examples
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.2. Generating the Design Example

Figure 18. Procedure
  1. In the Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard).
  2. Specify the Directory, Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings under Family, select Agilex™ 7 I-Series.
  6. Select the Target Device for your design.
  7. Click Finish.
  8. In the IP Catalog locate and add the Intel R-Tile Avalon® -ST Hard IP for PCI Express* .
  9. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  10. On the Top-Level Settings and PCIe* Settings tabs, specify the parameters for your IP variation.
    If you want to run PIPE Mode simulations, enable the Enable PIPE Mode Simulation parameter in the Top-Level Settings tab. For more details on PIPE Mode simulations, refer to Generating the Design Example with R-Tile Configured in PIPE Mode.
    If you want to generate the SR-IOV design example, perform the following steps to enable SR-IOV:
    1. On the Top-Level Settings tab, set the PCIe Hard IP Mode parameter to Gen5 1x16, interface - 1024 bit
    2. On the PCIe0 Settings tab, navigate to PCIe0 PCI Express/PCI Capabilities > PCIe0 Device > PCIe0 Multifunction and SR-IOV System Settings and:
      1. Check the Enable Multiple Physical Functions parameter.
      2. Set the Total Physical Functions (PFs) parameter to 2.
      3. Check the Enable SR-IOV Support parameter.
      4. Set the Total Virtual Functions of Physical Function 0 (PF0 VFs) parameter to 16.
      5. Set the Total Virtual Functions of Physical Function 1 (PF1 VFs) parameter to 16.
    3. On the PCIe0 Settings tab, navigate to PCIe0 Base Address Registers > PCIe0 PF0 BAR Configuration > PCIe0 PF0 BAR and:
      1. Set the BAR0 Type parameter to 64-bit prefetchable memory or 64-bit non-prefetchable memory or 32-bit non-prefetchable memory.
      2. Set the BAR0 Size parameter to any value other than N/A.
    4. Repeat steps i and ii for PCIe0 PF0 BAR above in the PCIe0 PF0 VF BAR section.
    5. On the PCIe0 Settings tab, navigate to PCIe0 Base Address Registers > PCIe0 PF1 BAR Configuration > PCIe0 PF1 BAR and:
      1. Set the BAR0 Type parameter to 64-bit prefetchable memory or 64-bit non-prefetchable memory or 32-bit non-prefetchable memory.
      2. Set the BAR0 Size parameter to any value other than N/A.
    6. Repeat steps i and ii for PCIe0 PF1 BAR above in the PCIe0 PF1 VF BAR section.
    7. On the PCIe0 Settings tab, navigate to PCIe0 PCI Express/PCI Capabilities > PCIe0 MSI-X > PCIe0 PF MSI-X > PCIe0 PF0 MSI-X and check the Enable MSI-X parameter.
    8. On the PCIe0 Settings tab, navigate to PCIe0 PCI Express/PCI Capabilities > PCIe0 MSI-X > PCIe0 PF MSI-X > PCIe0 PF1 MSI-X and check the Enable MSI-X parameter.
    9. On the PCIe0 Settings tab, navigate to PCIe0 Device Identification Registers and set the following parameters for the PCIe0 PF0 IDs and the PCIe0 PF1 IDs:
      • Vendor ID: 0x00001172
      • Device ID: 0x00000000
      • Revision ID: 0x00000001
      • Class Code: 0x00ff0000
      • Subsystem Vendor ID: 0x00001172
      • Subsystem Device ID: 0x00000000
  11. On the Currently Selected Design Example tab, make the following selections:
    1. For Currently Selected Design Example select the PIO, SR-IOV or Performance design example.
    2. For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
    3. For Generated HDL Format, only Verilog is available in the current release.
    4. For Target Development Kit, select the appropriate development kit.
      Note: If you select None, the generated design example targets the device you specified in Step 5 above. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file. You can also use the pin planner tool to make pin assignments.
      Note: If you select a development kit, the device on that board overwrites the device selected in the Quartus® Prime project if the devices are different.
      Note: For Currently Selected Example Design, select PIO/SRIOV or PERFORMANCE_DESIGN.
  12. Select Generate Example Design to create a design example that you can simulate and download to hardware. If you select one of the R-Tile development boards, the device on that board overwrites the device previously selected in the Quartus® Prime project if the devices are different. When the prompt asks you to specify the directory for your example design, you can accept the default directory, ./intel_rtile_pcie_ast_0_example_design, or choose another directory.
    Figure 19. IP Parameter Editor Screen for Generating Example Design
  13. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the example design.
  14. Close the current open project.
  15. Open the example design project. This is the new project that has been generated in the location specified in step 12.
  16. Compile the example design project to generate the .sof file for the complete example design.
  17. Close your example design project.
    Note that you cannot change the PCIe pin allocations in the Quartus® Prime project. However, to ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by this IP.

Section Content
Generating the Design Example with R-Tile Configured in PIPE Mode
Generating the Performance Design Example for TL Bypass Mode

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