Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public

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4.1.3. Register Packing

The GPIO IP core allows you to pack register into the periphery to save area and resource utilization.

You can configure the full-rate DDIO on the input and output path as a flip flop. To do so, add the .qsf assignments listed in this table.

Table 19.  Register Packing QSF Assignments
Path QSF Assignment
Input register packing set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>
Output register packing set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>
Output enable register packing set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register>
Note: These assignments do not guarantee register packing. However, these assignments enable the Fitter to find a legal placement. Otherwise, the Fitter keeps the flip flop in the core.