Intel® Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 7/07/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 I/O Overview 2. Intel® Stratix® 10 I/O Architecture and Features 3. Intel® Stratix® 10 I/O Design Considerations 4. Intel® Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Intel® Stratix® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide
1. Intel® Stratix® 10 I/O Overview x
1.1. Intel® Stratix® 10 I/O and Differential I/O Buffers 1.2. Intel® Stratix® 10 I/O Migration Support
2. Intel® Stratix® 10 I/O Architecture and Features x
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices 2.2. I/O Element Structure in Intel® Stratix® 10 Devices 2.3. Programmable IOE Features in Intel® Stratix® 10 Devices 2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices 2.5. External I/O Termination for Intel® Stratix® 10 Devices
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices x
2.1.1. Intel® Stratix® 10 I/O Standards Support 2.1.2. Intel® Stratix® 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Intel® Stratix® 10 Devices x
2.2.1. I/O Bank Architecture in Intel® Stratix® 10 Devices 2.2.2. I/O Buffer and Registers in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices x
2.3.1. Programmable Output Slew Rate Control 2.3.2. Programmable IOE Delay 2.3.3. Programmable Open-Drain Output 2.3.4. Programmable Bus Hold 2.3.5. Programmable Pull-Up Resistor 2.3.6. Programmable Pre-Emphasis 2.3.7. Programmable Differential Output Voltage 2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices x
2.4.1. RS OCT without Calibration in Intel® Stratix® 10 Devices 2.4.2. RS OCT with Calibration in Intel® Stratix® 10 Devices 2.4.3. RT OCT with Calibration in Intel® Stratix® 10 Devices 2.4.4. Dynamic OCT 2.4.5. Differential Input RD OCT 2.4.6. OCT Calibration Block in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices x
2.5.1. Single-Ended I/O Termination 2.5.2. Differential I/O Termination for Intel® Stratix® 10 Devices
2.5.2. Differential I/O Termination for Intel® Stratix® 10 Devices x
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 2.5.2.3. LVPECL Termination
3. Intel® Stratix® 10 I/O Design Considerations x
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
4. Intel® Stratix® 10 I/O Implementation Guides x
4.1. GPIO Intel® FPGA IP 4.2. Verifying Resource Utilization and Design Performance 4.3. GPIO Intel® FPGA IP Timing 4.4. GPIO Intel® FPGA IP Design Examples 4.5. Verifying Pin Migration Compatibility 4.6. IP Migration to the GPIO IP Core
4.1. GPIO Intel® FPGA IP x
4.1.1. Release Information for GPIO Intel® FPGA IP 4.1.2. GPIO Intel® FPGA IP Data Paths 4.1.3. Register Packing
4.1.2. GPIO Intel® FPGA IP Data Paths x
4.1.2.1. Input Path 4.1.2.2. Output and Output Enable Paths
4.3. GPIO Intel® FPGA IP Timing x
4.3.1. Timing Components 4.3.2. Delay Elements 4.3.3. Timing Analysis 4.3.4. Timing Closure Guidelines
4.3.3. Timing Analysis x
4.3.3.1. Single Data Rate Input Register 4.3.3.2. Full-Rate or Half-Rate DDIO Input Register 4.3.3.3. Single Data Rate Output Register 4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.4. GPIO Intel® FPGA IP Design Examples x
4.4.1. GPIO IP Core Synthesizable Intel® Quartus® Prime Design Example 4.4.2. GPIO IP Core Simulation Design Example
4.6. IP Migration to the GPIO IP Core x
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel® FPGA IP Reference x
5.1. GPIO Intel® FPGA IP Parameter Settings 5.2. GPIO Intel® FPGA IP Interface Signals
5.2. GPIO Intel® FPGA IP Interface Signals x
5.2.1. Shared Signals 5.2.2. Data Bit-Order for Data Interface 5.2.3. Data Interface Signals and Corresponding Clocks
1. Intel® Stratix® 10 I/O Overview
2. Intel® Stratix® 10 I/O Architecture and Features
3. Intel® Stratix® 10 I/O Design Considerations
4. Intel® Stratix® 10 I/O Implementation Guides
5. GPIO Intel® FPGA IP Reference
6. Intel® Stratix® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide

5.2. GPIO Intel® FPGA IP Interface Signals

Depending on parameter settings you specify, different interface signals are available for the GPIO IP core.
Figure 38.  GPIO IP Core Interfaces


Figure 39.  GPIO Interface Signals


Table 28.  Pad Interface SignalsThe pad interface is the physical connection from the GPIO IP core to the pad. This interface can be an input, output or bidirectional interface, depending on the IP core configuration. In this table, SIZE is the data width specified in the IP core parameter editor.
Signal Name Direction Description
pad_in[SIZE-1:0] Input

Input signal from the pad.
pad_in_b[SIZE-1:0] Input

Negative node of the differential input signal from the pad. This port is available if you turn on the Use differential buffer option.

pad_out[SIZE-1:0] Output Output signal to the pad.
pad_out_b[SIZE-1:0] Output

Negative node of the differential output signal to the pad. This port is available if you turn on the Use differential buffer option.

pad_io[SIZE-1:0] Bidirectional

Bidirectional signal connection with the pad.
pad_io_b[SIZE-1:0] Bidirectional

Negative node of the differential bidirectional signal connection with the pad. This port is available if you turn on the Use differential buffer option.

Table 29.  Data Interface SignalsThe data interface is an input or output interface from the GPIO IP core to the FPGA core. In this table, SIZE is the data width specified in the IP core parameter editor.
Signal Name Direction Description
din[DATA_SIZE-1:0] Input

Data input from the FPGA core in output or bidirectional mode. DATA_SIZE depends on the register mode:

  • Bypass or simple register— DATA_SIZE = SIZE
  • DDIO without half-rate logic— DATA_SIZE = 2 × SIZE
  • DDIO with half-rate logic— DATA_SIZE = 4 × SIZE
dout[DATA_SIZE-1:0] Output

Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode:

  • Bypass or simple register— DATA_SIZE = SIZE
  • DDIO without half-rate logic— DATA_SIZE = 2 × SIZE
  • DDIO with half-rate logic— DATA_SIZE = 4 × SIZE
oe[OE_SIZE-1:0] Input

OE input from the FPGA core in output mode with Enable output enable port turned on, or bidirectional mode. OE is active high. When transmitting data, set this signal to 1. When receiving data, set this signal to 0. OE_SIZE depends on the register mode:

  • Bypass or simple register— DATA_SIZE = SIZE
  • DDIO without half-rate logic— DATA_SIZE = SIZE
  • DDIO with half-rate logic— DATA_SIZE = 2 × SIZE
Table 30.  Clock Interface SignalsThe clock interface is an input clock interface. It consists of different signals, depending on the configuration. The GPIO IP core can have zero, one, two, or four clock inputs. Clock ports appear differently in different configurations to reflect the actual function performed by the clock signal.
Signal Name Direction Description
ck Input

In input and output paths, this clock feeds a packed register or DDIO if you turn off the Half Rate logic parameter.

In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter.

ck_fr Input

In input and output paths, these clocks feed the full-rate and half-rate DDIOs if your turn on the Half Rate logic parameter.

In bidirectional mode, the input and output paths use these clocks if you turn off the Separate input/output Clocks parameter.

ck_hr
ck_in Input

In bidirectional mode, these clocks feed a packed register or DDIO in the input and output paths if you specify both these settings:

  • Turn off the Half Rate logic parameter.
  • Turn on the Separate input/output Clocks parameter.
ck_out
ck_fr_in Input

In bidirectional mode, these clocks feed a full-rate and half-rate DDIOS in the input and output paths if you specify both these settings

  • Turn on the Half Rate logic parameter.
  • Turn on the Separate input/output Clocks parameter.

For example, ck_fr_out feeds the full-rate DDIO in the output path.

ck_fr_out
ck_hr_in
ck_hr_out
cke Input Clock enable.
Table 31.  Termination Interface SignalsThe termination interface connects the GPIO IP core to the I/O buffers.
Signal Name Direction Description
seriesterminationcontrol Input Input from the termination control block (OCT) to the buffers. It sets the buffer series impedance value.
parallelterminationcontrol Input Input from the termination control block (OCT) to the buffers. It sets the buffer parallel impedance value.
Table 32.  Reset Interface SignalsThe reset interface connects the GPIO IP core to the DDIOs.
Signal Name Direction Description
sclr Input Synchronous clear input. Not available if you enable sset.
aclr Input Asynchronous clear input. Active high. Not available if you enable aset.
aset Input Asynchronous set input. Active high. Not available if you enable aclr.
sset Input Synchronous set input. Not available if you enable sclr.
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