Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 7/07/2021
Public

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2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination

Differential HSTL, SSTL, HSUL, and POD inputs use LVDS differential input buffers. However, RD support is only available if the I/O standard is LVDS.

Differential HSTL, SSTL, HSUL, and POD outputs are not true differential outputs. These I/O standards use two single-ended outputs with the second output programmed as inverted.

Figure 18. Differential SSTL I/O Standard TerminationThis figure shows the details of Differential SSTL I/O termination on Intel® Stratix® 10 devices.


Figure 19. Differential HSTL I/O Standard TerminationThis figure shows the details of Differential HSTL I/O standard termination on Intel® Stratix® 10 devices.


Figure 20. Differential POD I/O Standard TerminationThis figure shows the details of Differential POD I/O termination on the Intel® Stratix® 10 devices.