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Key Advantages of Intel® Cyclone® 10 GX Devices
Summary of Intel® Cyclone® 10 GX Features
Intel® Cyclone® 10 GX Available Options
Intel® Cyclone® 10 GX Maximum Resources
Intel® Cyclone® 10 GX Package Plan
I/O Vertical Migration for Intel® Cyclone® 10 GX Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1 and Gen2 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel® Cyclone® 10 GX Device Overview
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Variable-Precision DSP Block
The Intel® Cyclone® 10 GX variable precision DSP blocks support fixed-point arithmetic and floating-point arithmetic.
Features for fixed-point arithmetic:
- High-performance, power-optimized, and fully registered multiplication operations
- 18-bit and 27-bit word lengths
- Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
- Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
- Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
- Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
- Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
- Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
- 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
- Biased rounding support
Features for floating-point arithmetic:
- A completely hardened architecture that supports multiplication, addition, subtraction, multiply-add, and multiply-subtract
- Multiplication with accumulation capability and a dynamic accumulator reset control
- Multiplication with cascade summation capability
- Multiplication with cascade subtraction capability
- Complex multiplication
- Direct vector dot product
- Systolic FIR filter
Usage Example | Multiplier Size (Bit) | DSP Block Resources |
---|---|---|
Medium precision fixed point | Two 18 x 19 | 1 |
High precision fixed or Single precision floating point | One 27 x 27 | 1 |
Fixed point FFTs | One 19 x 36 with external adder | 1 |
Very high precision fixed point | One 36 x 36 with external adder | 2 |
Double precision floating point | One 54 x 54 with external adder | 4 |
Device | Variable-precision DSP Block |
Independent Input and Output Multiplications Operator |
18×19 Multiplier Adder Sum Mode |
18×18 Multiplier Adder Summed with 36-bit Input |
|
---|---|---|---|---|---|
18×19 Multiplier |
27×27 Multiplier |
||||
10CX085 | 84 | 168 | 84 | 84 | 84 |
10CX105 | 125 | 250 | 125 | 125 | 125 |
10CX150 | 156 | 312 | 156 | 156 | 156 |
10CX220 | 192 | 384 | 192 | 192 | 192 |
Device | Variable-precision DSP Block |
Single Precision Floating-Point Multiplication Mode | Single-Precision Floating-Point Adder Mode | Single-Precision Floating-Point Multiply Accumulate Mode | Peak Giga Floating-Point Operations per Second (GFLOPs) |
---|---|---|---|---|---|
10CX085 | 84 | 84 | 84 | 84 | 76 |
10CX105 | 125 | 125 | 125 | 125 | 113 |
10CX150 | 156 | 156 | 156 | 156 | 140 |
10CX220 | 192 | 192 | 192 | 192 | 173 |