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Key Advantages of Intel® Cyclone® 10 GX Devices
Summary of Intel® Cyclone® 10 GX Features
Intel® Cyclone® 10 GX Available Options
Intel® Cyclone® 10 GX Maximum Resources
Intel® Cyclone® 10 GX Package Plan
I/O Vertical Migration for Intel® Cyclone® 10 GX Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1 and Gen2 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel® Cyclone® 10 GX Device Overview
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Intel® Cyclone® 10 GX Maximum Resources
Resource | Product Line | ||||
---|---|---|---|---|---|
10CX085 | 10CX105 | 10CX150 | 10CX220 | ||
Logic Elements (LE) (K) | 85 | 104 | 150 | 220 | |
ALM | 31,000 | 38,000 | 54,770 | 80,330 | |
Register | 124,000 | 152,000 | 219,080 | 321,320 | |
Memory (Kb) | M20K | 5,820 | 7,640 | 9,500 | 11,740 |
MLAB | 653 | 799 | 1,152 | 1,690 | |
Variable-precision DSP Block | 84 | 125 | 156 | 192 | |
18 x 19 Multiplier | 168 | 250 | 312 | 384 | |
Hard Floating-point Arithmetic | Yes | Yes | Yes | Yes | |
PLL | Fractional Synthesis | 2 | 4 | 4 | 4 |
I/O | 4 | 6 | 6 | 6 | |
12.5 Gbps Transceiver | 6 | 12 | 12 | 12 | |
GPIO 2 | 216 | 284 | 284 | 284 | |
LVDS Pair 3 | 84 | 118 | 118 | 118 | |
PCIe Hard IP Block | 1 | 1 | 1 | 1 | |
Hard Memory Interfaces | 1 | 2 | 2 | 2 |
2 The number of GPIOs does not include transceiver I/Os. In the Intel® Quartus® Prime Pro Edition software, the number of user I/Os includes transceiver I/Os.
3 Each LVDS I/O pair can be used as differential input or output.