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Key Advantages of Intel® Cyclone® 10 GX Devices
Summary of Intel® Cyclone® 10 GX Features
Intel® Cyclone® 10 GX Available Options
Intel® Cyclone® 10 GX Maximum Resources
Intel® Cyclone® 10 GX Package Plan
I/O Vertical Migration for Intel® Cyclone® 10 GX Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1 and Gen2 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel® Cyclone® 10 GX Device Overview
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PCS Protocol Support
Protocol | Data Rate (Gbps) | Transceiver IP | PCS Support |
---|---|---|---|
PCIe Gen2 x1, x2, x4 | 5.0 | Native PHY (PIPE) | Standard PCS |
PCIe Gen1 x1, x2, x4 | 2.5 | Native PHY (PIPE) | Standard PCS |
1000BASE-X Gigabit Ethernet | 1.25 | Native PHY | Standard PCS |
1000BASE-X Gigabit Ethernet with IEEE 1588v2 | 1.25 | Native PHY | Standard PCS |
10GBASE-R | 10.3125 | Native PHY | Enhanced PCS |
10GBASE-R with IEEE 1588v2 | 10.3125 | Native PHY | Enhanced PCS |
Interlaken (CEI-6G-SR/CEI-11G-SR) | 3.125 to 12.5 | Native PHY | Enhanced PCS |
SFI-S/SFI-5.2 | 6.25 | Native PHY | Enhanced PCS |
12G SDI | 11.88 | Native PHY | Enhanced PCS |
CPRI 6.0 (64B/66B) | 0.6144 to 6.144 | Native PHY | Enhanced PCS |
CPRI 4.2 (8B/10B) | 0.6144 to 6.144 | Native PHY | Standard PCS |
OBSAI RP3 v4.2 | 0.6144 to 6.144 | Native PHY | Standard PCS |
SD-SDI/HD-SDI/3G-SDI | 0.1436 to 2.97 | Native PHY | Standard PCS |
6 The 0.143 Gbps data rate is supported using oversampling of user logic that you must implement in the FPGA fabric.