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Key Advantages of Intel® Cyclone® 10 GX Devices
Summary of Intel® Cyclone® 10 GX Features
Intel® Cyclone® 10 GX Available Options
Intel® Cyclone® 10 GX Maximum Resources
Intel® Cyclone® 10 GX Package Plan
I/O Vertical Migration for Intel® Cyclone® 10 GX Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1 and Gen2 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel® Cyclone® 10 GX Device Overview
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FPGA General Purpose I/O
Intel® Cyclone® 10 GX devices offer highly configurable GPIOs. Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller.
The following list describes the features of the GPIOs:
- Consist of 3 V I/Os for high-voltage application and LVDS I/Os for differential signaling
- One 3 V I/O bank that supports up to 3 V I/O standards
- LVDS I/O banks that support up to 1.8 V I/O standards
- Support a wide range of single-ended and differential I/O interfaces
- LVDS speeds up to 1.434 Gbps
- Each LVDS pair of pins has differential input and output buffers, allowing you to configure the LVDS direction for each pair.
- Programmable bus hold and weak pull-up
- Programmable differential output voltage (VOD) and programmable pre-emphasis
- Series (RS ) and parallel (RT ) on-chip termination (OCT) for all I/O banks with OCT calibration to limit the termination impedance variation
- On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity
- Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture