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Key Advantages of Intel® Cyclone® 10 GX Devices
Summary of Intel® Cyclone® 10 GX Features
Intel® Cyclone® 10 GX Available Options
Intel® Cyclone® 10 GX Maximum Resources
Intel® Cyclone® 10 GX Package Plan
I/O Vertical Migration for Intel® Cyclone® 10 GX Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1 and Gen2 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel® Cyclone® 10 GX Device Overview
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I/O PLLs
The integer mode I/O PLLs are located in each bank of 48 I/Os. You can use the I/O PLLs to simplify the design of external memory and high-speed LVDS interfaces.
In each I/O bank, the I/O PLLs are adjacent to the hard memory controllers and LVDS SERDES. Because these PLLs are tightly coupled with the I/Os that need to use them, it makes it easier to close timing.
You can use the I/O PLLs for general purpose applications in the core such as clock network delay compensation and zero-delay buffering.
Intel® Cyclone® 10 GX devices support PLL-to-PLL cascading.