E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.7.4.3. Three 24.33024 Gbps channels with RS-FEC

You can place the first channel of your three channel to first_lane0 or first_lane1. You can choose any channel as a master channel from those three channels using the RS-FEC Clocking Mode parameter. For example, for first_lane0, you can select fec_dir_adp_clk_0, fec_dir_adp_clk_1, or fec_dir_adp_clk_2 as your master channel.

Figure 81. Three 24.33024 Gbps Channels with RS-FEC