2.11.12. 1588 PTP Interface

E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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2.11.12. 1588 PTP Interface

The E-Tile Hard IP for Ethernet Intel FPGA IP 1588 PTP Interface is available for 10G/25G designs when you turn on Enable IEEE 1588 PTP for 10G/25G channels in 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP variation. The 1588 Precision Time Protocol (PTP) timestamp information provided is as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard.

These signals are active only when your selected channel is configured to provide a MAC+PTP+PCS stack.

All 1-step and 2-step TX/RX Timestamp interface signals are common for both, basic and advanced PTP accuracy modes with the exception of these TOD interface signals:

In basic PTP accuracy mode: i_ptp_tod
In advanced PTP accuracy mode: i_sl_ptp_tx_tod/i_sl_ptp_tx_tod

All interface signals, except the TOD interface signals²⁹ and PTP ready signals³⁰, are clocked by the TX or RX clock.

TX clock represents i_sl_clk_tx clock when the asynchronous adapter is disabled and i_sl_async_clk_tx clock when the asynchronous adapter is enabled.
RX clock represents i_sl_clk_rx clock when the asynchronous adapter is disabled and i_sl_async_clk_rx clock when the asynchronous adapter is enabled.

The signal names are standard Avalon® streaming interface signals with slight differences to indicate the variations. For example:

For 100GE channel or single channel 10GE/25GE: i_ptp_ins_ets
For selected 10GE/25GE channel: i_sl_ptp_ins_ets[(n*width)-1:0]

Table 46. Signals of the 1-Step TX Timestamp Interface
Signal Name	Width	Description
`i_ptp_ins_ets` `i_sl_ptp_ins_ets[n-1:0]`	1	Egress timestamp into the current TX Packet on the respective channel. Valid only when the TX valid and TX SOP signals are asserted. Do not use when the TX skip CRC signal (e.g. `i_tx_skip_crc`) is asserted. The CRC for the TX packet must be recalculated after the egress timestamp is written. Do not use when the residence time timestamp signal (e.g. `i_ptp_ins_cf`) is asserted. You cannot update residence time and insert an egress timestamp on the same packet. Set the position of the PTP timestamp field in the TX packet (e.g. `i_ptp_ts_offset`) to the byte position of the start of the timestamp field in the PTP header. Set the format for the PTP 1-step operation (e.g. `i_ptp_ts_format`) to the desired timestamp format. If the selected timestamp format requires a 96b timestamp, set the PTP correction field in the TX packet (e.g. `i_ptp_cf_offset`) to the byte position of the start of the correction field in the PTP header.
`i_ptp_ins_cf` `i_sl_ptp_ins_cf[n-1:0]`	1	Residence time timestamp into the correction field in the current TX packet on the respective channel. Valid only when the TX valid and TX SOP signals are asserted. Do not use when the TX skip CRC signal (e.g. `i_tx_skip_crc`) is asserted. The CRC for the TX packet must be recalculated after the residence time is written. Do not use when the egress time timestamp signal (e.g. `i_ptp_ins_ets`) is asserted. You cannot update residence time and insert an egress timestamp on the same packet. Provide the core with the ingress timestamp of the current packet (e.g. assert `i_ptp_tx_its`) when it entered the system, so that a residence time can be calculated. Set the position of the PTP correction field in the TX packet (e.g. `i_ptp_cf_offset`) to the byte position of the start of the correction field in the PTP header. Note: If the PTP packet resides in the system for more than 4 seconds, the correction field shows a mismatched value with a very large number. Set `i_ptp_ts_format` to 0.
`i_ptp_zero_csum` `i_sl_ptp_zero_csum[n-1:0]`	1	Overwrites the checksum in a UDP packet carried inside the current TX packet with zeros. Valid only when the TX valid and TX SOP signals are asserted. Do not use when the TX skip CRC signal (e.g. `i_tx_skip_crc`) is asserted. The CRC for the TX packet must be recalculated after the checksum is changed. Do not use when the update extended bytes field signal (e.g `i_ptp_update_eb`) is asserted. You cannot set a UDP checksum to 0, and update an extension field to cancel out checksum changes on the same packet. Set the position of the UDP checksum field in the TX packet (e.g. `i_ptp_csum_offset`) to the byte position of the start of the UDP checksum in the TX packet.
`i_ptp_update_eb` `i_sl_ptp_update_eb[n-1:0]`	1	Overwrites the extended bytes field in an IPv6 packet carried inside the current TX packet with a value that cancels out changes to the checksum due to changes to the UDP packet. Valid only when the TX valid and TX SOP signals are asserted. Do not use when the TX skip CRC signal (e.g. `i_tx_skip_crc`) is asserted. The CRC for the TX packet must be recalculated after the checksum is changed. Do not use when the overwrite a UDP checksum with zeros signal (e.g. `i_ptp_zero_csum`) is asserted. You cannot set a UDP checksum to 0, and update an extension field to cancel out checksum changes on the same packet. Set the position of the first byte of the extended bytes field in the TX packet (e.g. `i_ptp_eb_offset`) to the byte position of the start of the UDP checksum in the TX packet.
`i_ptp_ts_format` `i_sl_ptp_ts_format[n-1:0]`	1	Format of the PTP 1-step operation on the respective channel. 0: Use IEEE 1588v2 timestamp and correction field formats (96 bits) 1: Use IEEE 1588v1 timestamp format (64 bits) Valid only when either the egress time timestamp signal (`i_ptp_ins_ets`) or the residence time timestamp signal ( `i_ptp_ins_cf`), and the TX valid signal, and SOP signal are asserted. When `i_ptp_ins_cf` is asserted, this port must be set to 0. The correction field is only applicable to IEEE 1588v2 format.
`i_ptp_ts_offset` `i_sl_ptp_ts_offset[(n*16)-1:0]`	16	Position of the PTP timestamp field in the current TX packet. Valid only when the TX valid and TX SOP signals are asserted. It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0. The IEEE 1588v2 PTP timestamp field is 10 octets long (80 bits), and the IEEE 1588v1 timestamp is 8 octets long (64bits), starting from the position given by the offset. Because the IEEE 1588v2 timestamps are actually 96 bits long, the lower 16 bits of the timestamp are placed in the lower 2 octets of the correction field. CAUTION: You must set the offset to a position within the TX packet, or the PTP insertion operation fails. You must not also overlap the PTP fields.
`i_ptp_cf_offset` `i_sl_ptp_cf_offset[(n*16)-1:0]`	16	Position of the PTP correction field in the current TX packet. Valid only when the TX valid and TX SOP signals are asserted. It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0. The PTP correction field is 8 octets long, starting from the position given by the offset. When 96-bit timestamps are used, the MAC places the lower 16 bits of the timestamp in the lower 2 octets of the correction field. CAUTION: You must set the offset to a position within the TX packet, or the PTP insertion operation fails. You must not also overlap the PTP fields.
`i_ptp_csum_offset` `i_sl_ptp_csum_offset[(n*16)-1:0]`	16	Position of the first byte of a UDP checksum field in the current TX packet. Valid only when the checksum overwrite in a UDP packet (e.g. `i_ptp_zero_csum`), TX valid, TX SOP signals are asserted. It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0. CAUTION: You must set the offset to a position within the TX packet, or the PTP insertion operation fails. You must not also overlap the PTP fields.
`i_ptp_eb_offset` `i_sl_ptp_eb_offset[(n*16)-1:0]`	16	Position of the first byte of extended bytes field in the current TX packet. Valid only when the extended bytes overwrite in an IPv6 packet (e.g. `i_ptp_update_eb`), TX valid, TX SOP signals are asserted. It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0. CAUTION: You must set the offset to a position within the TX packet, or the PTP insertion operation fails. You must not also overlap the PTP fields.
`i_ptp_tx_its` `i_sl_ptp_tx_its[(n*96)-1:0]`	96	Ingress timestamp for a TX packet that requires a residence time calculation (e.g. `i_ptp_ins_cf` = 1). This timestamp is the time at which the packet arrives in the system. The TX MAC compares this time to the time at which the packet leaves the system to generate a residence time. You must set the `i_ptp_ts_format` to 0. Residence time calculation/correction is only applicable to IEEE 1588v2 format. Valid only when the TX valid and TX SOP signals are asserted.

Table 47. Signals of the 2-Step TX Timestamp InterfaceUse the 2-step TX Timestamp to request for 2-step TX Timestamps when a packet is transmitted.
Signal Name	Width	Description
`i_ptp_ts_req` `i_sl_ptp_ts_req[n-1:0]`	1	Request a 2-step timestamp signal for the current TX packet. When asserted, generates a TX timestamp for the current packet. Valid only when the TX valid and TX SOP signals are asserted.
`i_ptp_fp` `i_sl_ptp_fp[(n*8)-1:0]`	8	Fingerprint signal for current TX packet. Assigns an 8-bit fingerprint to a TX packet that is being transmitted, so that the 2-step or 1-step PTP timestamp associated with the TX packet can be identified. The timestamp returns with the same fingerprint. Use a range of fingerprints from 0..31 or larger, to avoid the possibility of assigning the same fingerprint to 2 TX packets that are being processed. Choose an easy-to-decode null fingerprint for any packets that do not require an egress timestamp. For example, if you use a range of 0..31, make 32 the null fingerprint. Valid only when the TX valid and TX SOP signals are asserted.
`o_ptp_ets_valid` `o_sl_ptp_ets_valid[n-1:0]`	1	1-step or 2-step egress timestamp valid signal. When asserted, the fingerprint and egress timestamp signals present valid output on this cycle. This signal is asserted after the timestamp is generated in one of these scenarios: You assert `i_ptp_ts_req` to request 2-step timestamp. You assert `i_ptp_ins_ets` to request 1-step timestamp insertion.
`o_ptp_ets` `o_sl_ptp_ets[(n*96)-1:0]`	96	2-step or 1-step egress timestamp signal. This port presents an egress timestamp for the TX Packet that was transmitted with the fingerprint given by `o_ptp_ets_fp`. Following conditions apply to this signal: Valid only when the egress timestamp valid (`o_ptp_ets_valid`) signal is asserted. The timestamp is in 1588v2 format (96b). This corresponds to the generated timestamp when you assert `i_ptp_ts_req` to request 2-step timestamp or when you assert `i_ptpt_ins_ets` to request 1-step timestamp insertion. The timestamp is for the packet whose fingerprint matches the fingerprint with the egress timestamp. All timestamps are referenced to the copy of the Time-of-Day provided to the IP core through the `i_ptp_tod` port.
`o_ptp_ets_fp` `o_sl_ptp_ets_fp[(n*8)-1:0]`	8	Fingerprint for the current 2-step or 1-step egress timestamp. You can use the fingerprint to determine which TX packet the timestamp belongs to. Valid only when the egress timestamp valid signal ( `o_ptp_ets_valid`) is asserted.

Table 48. Signals of the Time of Day InterfaceThe time of day interface allows the core to reference all of its timestamps to the time of day as it is known locally.
Signal Name	Width	Description
`i_ptp_tod`	96	When you set the PTP Accuracy Mode to Basic Mode, this signal presents the current Time of Day, according to the local clock, to the Ethernet IP core. All channels in the same IP core share the same ToD port. When your design implements multiple IP cores, each IP core requires a ToD IP. The timestamp is in IEEE 1588v2 format (96b).
`i_sl_ptp_tx_tod[(n*96)-1:0]`	96	When you set the PTP Accuracy Mode to Advanced Mode, represents the TX Time of Day, according to the local clock. The timestamp is in IEEE 1588v2 format (96 bits).
`i_sl_ptp_rx_tod[(n*96-1):0]`	96	When you set the PTP Accuracy Mode to Advanced Mode, represents the RX Time of Day, according to the local clock. The timestamp format is in IEEE 1588v2 format (96 bits).

Table 49. Signals of the RX Timestamp InterfaceThe RX Timestamp interface allows each channel to provide RX timestamps when packets arrive.
Signal Name	Width	Description
`o_ptp_rx_its` `o_sl_ptp_rx_its[(n*96)-1:0]`	96	Ingress RX timestamp signal. Presents the ingress timestamp for the incoming RX packet on the respective channel. Valid only when the RX valid and RX SOP signals are asserted. The timestamp is in 1588v2 format (96b).

Table 50. Signals of the PTP Status InterfaceThe PTP Status interface lets applications using PTP functions know when the PTP timestamp logic is ready for use.
Signal Name	Width	Description
`o_tx_ptp_ready` `o_sl_tx_ptp_ready[n-1:0]`	1	TX PTP ready signal. When asserted, the core to ready to request for TX PTP functions on the respective channel.
`o_rx_ptp_ready` `o_sl_rx_ptp_ready[n-1:0]`	1	RX PTP ready signal. When asserted,the RX PTP logic ready for use on the respective channel. After reset and PMA adaptation, the signal gets asserted after link partner sends up to 20 Ethernet packets.

²⁹ The applicable TOD interface signals: i_ptp_tod in the basic PTP accuracy mode, i_sl_ptp_tx_tod/i_sl_ptp_rx_tod in the advance PTP accuracy mode.

³⁰ The applicable PTP ready signals: o_tx_ptp_ready/o_sl_tx_ptp_ready and o_rx_ptp_ready/o_sl_rx_ptp_ready.

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E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

2.11.12. 1588 PTP Interface