E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.12.3.4. IPG Words to remove per Alignment Marker Period

Offset: 0x406

IPG Words to remove per Alignment Marker Period Fields

Bit Name Description Access Reset
15:0 ipg_col_rem IPG_COL_REM

16b value that sets the number of IPG words that can be removed during an alignment marker period for a fully occupied link to make space for alignment markers. This parameter can also be used to scale IPG in ppm increments for rate balance.

  • After power-on, ipg_col_rem is set to 16'd20
  • After i_cfg_rst_n, ipg_col_rem is set to the standard value required for the selected line rate, plus the value of the module parameter ipg_removed_per_am_period.
RW 0x14