Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Discontinuation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) Loops Viewer Pane A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A.3.2. Loops Viewer (Alpha)

Use the Loops Viewer in the High-Level Design Reports to see the behavior of both implicit and explicit loops in your component and task functions. The Loops Viewer shows the behavior as a color-coded bar graph.

Alpha: As an alpha-level tool, the Loops Viewer is subject to some restrictions. Refer to Known Issues and Workarounds in the Intel® High Level Synthesis Compiler Pro Edition Release Notes for details.

By default, the Loops Viewer shows the visualization for one iteration (trip count of 1) of the loops, unless the loop is defined in your code with a constant number of iterations. You can adjust the number of displayed iterations and update the viewer to see how different trip counts for loops affect your component.

To access this tool report, click Throughput Analysis > Loops Viewer.

The Loops Viewer has the following panes:
  • Loops List

    The Loops List pane shows a list of the explicit and implicit loops identified by the compiler in your design.

    Click entries in the Loops List pane to focus the graphs shown in the Loops Viewer pane on a loop in your design, or click System to have all loops in your design show in the Loops Viewer pane.

  • Bottlenecks

    This pane does not provide any information in the Loops Viewer.

    To see information about loop bottlenecks, use the Bottlenecks pane in the Loop Analysis Report. For details about this report, refer to Loop Analysis Report.

  • Code view

    The code view pane lets you view all the code associated with your design.

  • Details

    When you click a row in the Loops Viewer pane, the Details pane provides any additional details if they are available.

Loops Viewer Pane

The Loops Viewer pane is split into the following parts:

  • The left part shows labels for loops and their parts, and the start and end cycle for the loop parts. This part also shows the number of trip counts displayed for a loop.

    To adjust the number of trip counts displayed for a loop, change the value in the Trip Count field for a loop and click Update.

    You might need to scroll left and right to see the Trip Count fields and the Update button.

  • The right part shows the duration (in number of clock cycles) of loop invocations and loop iterations as horizontal bars on a graph, similar to the presentation of Gantt charts.
    The horizontal bars are color-coded as follows:
    Table 7.  Loops Viewer Color Coding
    Color Description
    Black bars show the length of a loop invocation.

    A loop can be invoked multiple times when your design runs.

    Pink bars show the length of a loop iteration.

    A loop iteration is one execution of the body of your loop. One loop invocation typically results in more than one loop iteration.

    Light-pink bars show speculated loop iterations.

    Speculated iterations are loop iterations that are initiated while the loop exit condition is being calculated. They help enable more efficient loop pipelining in your component.

    For more information about speculated iterations, refer to Loop Iteration Speculation (speculated_iterations Pragma) in the Intel High Level Synthesis Compiler Pro Edition Reference Manual .

    Blue bars show the execution of logic outside of the innermost loop body, including loop control logic created by the compiler.
    Light-blue bars show handshaking registers added by the compiler.
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