Intel® High Level Synthesis Compiler Pro Edition: User Guide

Download PDF
ID 683456
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Discontinuation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A.1. Reviewing the Summary Report

The Summary Report gives you a quick overview of the results of compiling your design including a summary of each component in your design and a summary of the estimated resources that each component in your design uses.

The Summary report is divided into the following sections based on the order of compilation:
  • Compile Info
  • Functions
  • Clock Frequency Summary
  • Quartus Estimated Resource Utilization Summary
  • HLS Estimated Resource Utilization Summary
  • Warnings Summary



Compile Info

The Compile Info section shows general information about the compile including the following items:
  • Name of the project
  • Target FPGA family and device
  • HLS compiler version
  • Quartus® Prime version
  • The command that was used to compile the design
  • The date and time at which the reports are generated

Functions

For overloaded and templated functions in your hardware design, this section of the Summary Report shows you the short names generated by the Intel® HLS Compiler for the functions to prevent name collisions.

These short names are used in other parts of the High Level Design Report.

The Synthesized Function Name Mapping section does not show testbench functions. Only functions that are synthesizable to hardware are shown.

Clock Frequency Summary

After you compile your design with Quartus® Prime software, the Clock Frequency Summary shows the following:
  • Quartus Fitter Clock Frequency
  • Compiler Target Frequency (MHz)
  • Compiler estimated frequency (MHz)

The Quartus Fitter clock frequency is the maximum clock frequency that can be achieved for the design. When the compiler estimates a lower frequency than the targeted frequency, the frequency value is highlighted in red.

Both the Functions section and Clock Frequency Summary display the target clock frequency applied at the source on the component. When the values of the source is different than the compilation flag you applied, the Clock Frequency Summary Compiler Target Frequency shows “Various” instead of reporting a number.

Quartus Estimated Resource Utilization Summary

After you compile your design with Quartus® Prime software, the Quartus Estimated Resource Utilization Summary section shows the total area utilization both for the entire design, and for each component individually. There is no breakdown of area information by source line.

Function Summary

When you compile your design to target Intel Agilex® 7 or Stratix® 10 devices, this section of the report indicates whether a function in your design uses a modified handshaking protocol.

You can control the use of the modified handshaking protocol with the --hyper-optimized-handshaking option of the i++ command.

HLS Estimated Resource Utilization Summary

The HLS Estimated Resource Utilization Summary section shows a summary of the estimated resources used by each component in your design, as well as the total resources used for all components.

Warnings Summary

The Warnings Summary section shows the compiler warnings generated during the compilation.

Level Two Title