Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Discontinuation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report Loop List Pane Loop Analysis Pane Bottlenecks Pane A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A.3.1. Loop Analysis Report

The Loops Analysis report in the High-Level Design Reports (<result>.prj/reports/report.html) contains information about all the loops (coalesced, unrolled, and fused loops) in your design and their unroll statuses. This report helps you examine whether the Intel® HLS Compiler Pro Edition can maximize the throughput of your component.

To access the report, click Throughput Analysis > Loop Analysis.

The Loop Analysis report has the following panes:
  • Loop List

    Refer to Loop List Pane for details.

  • Loop Analysis

    Refer to Loop Analysis Pane for details.

  • Bottlenecks

    Refer to Bottlenecks Pane for details.

  • Code view

    When you click a link under Source Location in the Loop Analysis pane, the code view pane highlights the statement in your code that analysis applies to.

  • Details

    When you click a row in the Loop Analysis pane, the Details pane provides additional details.

Loop List Pane

The left-hand Loop List pane displays the following types of loops:

  • Fused loops
  • Fused subloops
  • Coalesced loops
  • Fully unrolled loops
  • Partial unrolled loops
  • Regular loops

Loop Analysis Pane

The Loops Analysis report captures the following key performance metrics on all blocks:

  • Source Location: Indicates the loop location in the source code.
  • Pipelined: Indicates whether the body of a loop is pipelined. Pipelining allows for many data items to be processed concurrently (in the same clock cycle) while making efficient use of the hardware in the datapath by keeping it occupied.
  • II: Shows the sustainable initiation interval (II) of the loop. Processing data in loops is an additional source of pipeline parallelism. When you pipeline a loop, the next iteration of the loop begins before previous iterations complete.

    Dependencies between loop iterations can affect II. The Intel® HLS Compiler automatically identifies dependencies between iterations and builds hardware to resolve dependencies while minimizing the II.

  • Scheduled f MAX : Shows an early estimate of the maximum clock frequency (fMAX) at which the loop operates. This estimate does not account for the effects of placing and routing.
  • Latency: Shows the number of clock cycles a loop takes to complete one or more instructions. Typically, you want to have low latency. However, lowering latency often results in decreased fMAX.
  • Speculated Iterations: Shows the loop speculation. Loop speculation is an optimization technique that enables more efficient loop pipelining by allowing future iterations to be initiated before determining whether the loop was exited already.

    For more information, refer to Loop Iteration Speculation (speculated_iterations Pragma) in the Intel HLS Compiler Reference Manual.

  • Max Interleaving Iterations: Indicates the number of interleaved invocations of an inner loop that can be executed simultaneously.

    For more information, refer to Loop Interleaving Control (max_interleaving Pragma) in the Intel HLS Compiler Reference Manual.

Bottlenecks Pane

Bottlenecks in a loop mean that one or more loop-carried dependencies cause the loop to have an II greater than 1 or cause the fMAX of your component to be lowered to achieve a loop II of 1.

The Bottlenecks pane identifies the following categories of loop bottlenecks in your components and tasks:

  • fMAX-reduction, II-increase, or both
  • Compiler-applied bottlenecks (private copies set to 1 on local memory)
  • Bottlenecks caused due to the pragmas or attributes that you apply to a loop
  • Concurrency-limiter bottleneck
You can also review the following High-Level Design Report tools for additional information about bottlenecks in your components and tasks:
  • System Viewer

    The System Viewer provides information about the isolated failing path and bottleneck type.

  • Schedule Viewer (Beta)

    The Schedule Viewer displays the bottleneck path for variables.

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