Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Discontinuation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A.2.1. System Viewer

The System Viewer is an interactive view of your system as a hierarchy of block diagrams of how the compiler constructed your component. These diagrams can help you understand how data flows through your component.

Access system-, function-, block-, and cluster-level views of your component by selecting Views > System Viewer in the High Level Design Reports menu.

The System Viewer represents your component and tasks as a system of functions. Each function is divided into a set of blocks. Inside each block is a set of non-branching instructions that covers your code and the compiler loop orchestration optimization. The connections between blocks show the execution flow of your component.

To save the amount of control handshaking infrastructure needed when synthesizing your design, the Intel® HLS Compiler Pro Edition groups instructions within a block into groups called clusters. For more information about clusters, refer to "Clustering the Datapath" in the Intel® HLS Compiler Best Practices Guide .

A branch node indicates the next block to go to and the condition required to go to that block.

The System Viewer is divided into two main panes: Graph List and Graph View. Clicking on different entries in the Graph List shows you different views of your component.



The different views available are as follows:.
  • System View

    The System View of the System Viewer provides a high-level view of components and tasks in your system.

  • Function View

    The Function views of the System Viewer show the blocks inside your component and any tasks. A function appears in this view if it is declared as component or launched as a task function. Other called functions are automatically inlined.

    Click a function name in the Graph List of the System Viewer to see the function view.

  • Block View

    The Block views of the System Viewer show stallable operations in your component and task functions, and the clusters and their connections.

  • Cluster View

    The Cluster views of the System Viewer shows the contents of clusters in your components.

Clicking on an element displays details about the element in the Details pane below Graph List and Graph Viewer panes and highlights connections to and from the element.

You can control the zoom of the diagram in the Graph Viewer pane using your mouse scroll wheel or equivalent touchpad gesture.


Section Content
Reviewing System Information
Reviewing Function Information
Reviewing Block Information
Reviewing Cluster Information

Level Two Title