Visible to Intel only — GUID: ewa1464368561352
Ixiasoft
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
Visible to Intel only — GUID: ewa1464368561352
Ixiasoft
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
The Intel® HLS Compiler Pro Edition has built-in macros that you can use to customize your code to create flow-dependent behaviors.
Tool Invocation | __INTELFPGA_COMPILER__ |
---|---|
g++ or cl | Undefined |
i++ -march=x86-64 | 2410 |
i++ -march="<FPGA_family_or_part_number>" | 2410 |
Tool Invocation | HLS_SYNTHESIS | |
---|---|---|
Testbench Code | HLS Component Code | |
g++ or cl | Undefined | Undefined |
i++ -march=x86-64 | Undefined | Undefined |
i++ -march="<FPGA_family_or_part_number>" | Undefined | Defined |