Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Discontinuation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A.2.1.4. Reviewing Cluster Information

Use the Cluster Views in the System Viewer report to examine the data path of computations within a cluster. The Intel® HLS Compiler Pro Edition groups instructions into clusters to reduce the amount of handshaking logic required when synthesizing your component.

For a description of clusters, review " Clustering the Datapath " in the Intel® HLS Compiler Pro Edition Best Practices Guide .

A cluster starts with an entry node and ends with an exit node. These nodes perform handshaking with logic outside of the cluster.

For a stall-free cluster, the exit node of the cluster has a FIFO with a depth greater than or equal to the latency of the cluster. This FIFO stores any in-flight data that needs to be passed outside of the cluster. To see the size of the cluster exit FIFO, click the exit node and see the information in the Details pane.

If your design contains loops, you see loop orchestration nodes (labeled as Loop Orch) and variable nodes as well as computation nodes. The loop orchestration nodes and variable nodes are shown along with their Feedback nodes.

The compiler generates the loop orchestration nodes to pipeline your loop to increase the performance.

A variable node corresponds to a variable that has a loop-carried dependency in your design. A variable node goes through various computation logic and finally feeds to a feedback node that connects back to the variable node. This connection shows that the new value of the variable is passed to the next iteration.

Look for loop-carried variables that have a long latency to the feedback nodes as they can be the initiation interval (II) bottlenecks. See the Loop Analysis report to reflect the II bottleneck.

The feedback node has a FIFO to store in-flight values of the variable in different iterations of the loop and has a size equal to the dependency distance multiplied by the II. The dependency distance is the number of iterations between successive load/store operations that depend on each other.

In a Cluster View, you can find the size of the cluster exit FIFO by clicking the exit node and looking at the Details pane. You can also find the size of the cluster exit FIFO in a Block View by clicking the exit node and looking at the Details pane.

Click a cluster in the Graph List pane to see that cluster in the Graph View pane.

Click nodes in the Cluster View pane to see details about that node as well as highlight the connections for the node inputs and outputs. For stallable nodes, the latency value provided in the details is an estimate. For more accurate latency values, run simulation on your component.



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