Intel® FPGA Power and Thermal Calculator User Guide

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Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Overview of the Intel® FPGA Power and Thermal Calculator 2. Setting Up the Intel® FPGA Power and Thermal Calculator 3. Intel® FPGA Power and Thermal Calculator Graphical User Interface 4. Intel® FPGA Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator 6. Intel® FPGA Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Intel® FPGA Power and Thermal Calculator x
1.1. Intel® FPGA PTC Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Intel® FPGA Power and Thermal Calculator x
2.1. Availability 2.2. Obtaining the Standalone Intel® FPGA Power and Thermal Calculator 2.3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 2.4. Power Analysis for Dual-Core 1SG10M Intel® Stratix® 10 Devices
2.3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
3.1. Intel® FPGA PTC Select Family Dialog Box 3.2. Intel® FPGA PTC Basic GUI Components
3.2. Intel® FPGA PTC Basic GUI Components x
3.2.1. Intel® FPGA PTC Data Entry Pages 3.2.2. Intel® FPGA PTC Field Types 3.2.3. Intel® FPGA PTC Input Field Dependencies 3.2.4. Intel® FPGA PTC Data Entry Error Messages
4. Intel® FPGA Power and Thermal Calculator Pages x
4.1. Intel® FPGA PTC - Power Summary 4.2. Intel® FPGA PTC - Common Page Elements 4.3. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows 4.4. Intel® FPGA PTC - Main Page 4.5. Intel® FPGA PTC - Logic Page 4.6. Intel® FPGA PTC - RAM Page 4.7. Intel® FPGA PTC - DSP Page 4.8. Intel® FPGA PTC - Clock Page 4.9. Intel® FPGA PTC - PLL Page 4.10. Intel® FPGA PTC - I/O Page 4.11. Intel® FPGA PTC - I/O-IP Page 4.12. Intel® FPGA PTC - Transceiver Page 4.13. Intel® FPGA PTC - HPS Page 4.14. Intel® FPGA PTC - Crypto Page ( Intel® Agilex™ Devices with Crypto Blocks Only) 4.15. Intel® FPGA PTC - HBM Page ( Intel® Stratix® 10 Devices Only) 4.16. Intel® FPGA PTC - Thermal Page 4.17. Intel® FPGA PTC - Report Page
4.12. Intel® FPGA PTC - Transceiver Page x
4.12.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator x
5.1. Toggle Rate 5.2. I/O Bank Allocation
1. Overview of the Intel® FPGA Power and Thermal Calculator
2. Setting Up the Intel® FPGA Power and Thermal Calculator
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface
4. Intel® FPGA Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator
6. Intel® FPGA Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

4.16. Intel® FPGA PTC - Thermal Page

The Thermal page of the Intel® FPGA Power and Thermal Calculator ( Intel® FPGA PTC) allows you to enter temperature requirements for your design and displays thermal power and thermal analysis information.
Note: To achieve correct power and thermal calculations, ensure that your design and all input values are entered accurately and correctly.

Thermal Page for Intel® Agilex™ Devices

On the Main worksheet, verify that Power Characteristics is set to Maximum, and then select the desired Calculation mode from the drop-down menu on the Main or Thermal page.

Figure 25. Thermal Page of the Intel® FPGA Power and Thermal Calculator— Intel® Agilex™

In the above figure, input parameters are circled in blue and reporting fields are circled in red.

Table 22.  Input Parameter Information
Parameter Description
Calculation Mode Specifies the calculation mode for the thermal solver to use. The available choices are:
  • Use a constant junction temperature. The Intel® FPGA PTC assumes uniform temperature across the dies.

    If you choose this mode, you can enter the junction temperature on the Main page or on the Thermal page.

    Note: The power calculated in the Use a constant junction temperature mode is not representative of actual power during use. It is unlikely that all components of the die are at uniform temperature during normal operation. For more representative power, use the other calculation modes that utilize the thermal calculator.
  • Find cooling solution for maximum junction temperature limit. The Intel® FPGA PTC finds the Tcase, a cooling solution ΨCA, and the power of all dies, assuming that no die can exceed the specified maximum TJ.

    If you choose this mode, enter maximum TJ and ambient temperature values.

  • Find available thermal margin for cooling solution. The Intel® FPGA PTC finds the thermal parameters for a known cooling solution and ambient temperature.

    If you choose this mode, enter values for the ambient temperature and ΨCA.

  • Find ambient temperature for specified cooling solution. The PTC finds the necessary ambient temperature for a given cooling solution and maximum TJ.

    If you choose this mode, Enter the ΨCA and the maximum TJ appropriate for the design.

Apply Additional Margin

Specifies, as a percentage, the amount of additional margin to apply to detailed thermal analysis results.

The default value is 0%. Valid values are 0-25%. The recommended margin for Intel® Agilex™ devices is 10%.

Consult your Intel Field Application Engineer (FAE) if you require additional guidance on margin power.

Note:
  1. Setting a non-zero margin causes the total power value on the Thermal page to be higher than the power reported elsewhere in the PTC.
  2. If you import a .ptc file from an earlier version of the Intel® FPGA PTC, which has the Apply Recommended Margin parameter set to Yes, the current version of the PTC interprets this as an Apply Additional Margin setting of 10%
TSD Mode Indicates the method by which sensor temperatures are reported. This parameter has no effect on maximum junction temperature or temperature margin.
Junction temperature, TJ (°C)

Allows you to specify the junction temperature for all dies in the package.

This field is available only when the selected Calculation mode is Use a constant junction temperature.

Ambient Temp, TA (°C) Allows you to specify the temperature of the air that is cooling the device.
Max. Junction Temp, TJ-MAX (°C) Allows you to specify the maximum junction temperature that no part of any die in the package should exceed.
Cooling Solution ΨCA(°C/W) Allows you to specify the cooling solution when you have selected the Use a constant junction temperature, Find available thermal margin for cooling solution, or Find ambient temperature for specified cooling solution calculation mode.
Table 23.  Max. ΨJC and Recommended Cooling Solution
Column Heading Description
Max. ΨJC(°C/W) ψJC is the thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. This field shows the maximum ΨJC among all dies, assuming the recommended ΨCA value below.
Recommended ambient Temperature TA(°C) TA is the recommended ambient temperature for the recommended cooling solution.
Recommended cooling solution ΨCA(°C/W) ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature.
Total Power (W) The total power consumption.

Table 24.  Thermal Margin Report Table
Column Heading Description
Die The die for which margin is reported:
  • FPGA Core: The margin for the FPGA core.
  • HSSI_x_y: The margin for the specified high-speed serial interface (HSSI) die.
Power (W) The thermal power dissipated by the specified die. This is the power used in the thermal analysis.
Note: The power listed on the Thermal page is currently pessimistic; the overall total power reported does not match the total on-chip power dissipation on the Power Summary page.
Margin Temperature (Δ°C) The calculated temperature margin in °C for the specified die, relative to the maximum TJ.
Power (ΔW) The amount of power in watts that can be added to the specified die, before reaching its maximum TJ.

Temperature margins are calculated relative to a designated maximum junction temperature, TJ. It is possible that one or more dies may have zero temperature margin, because the solution is calculated for that maximum TJ. The calculated power margins indicate the power buffer available before the maximum TJ is exceeded, assuming the same cooling conditions. The calculated power value provides only an approximate estimate of power that can be added to the specific die before reaching its maximum TJ. The actual margin depends on the specific subsystem to which the power is added. Note that any increase or decrease in power changes the required cooling solution.

Table 25.  Temperature Target Report Table
Column Heading Description
Monitor Location The die for which the temperature is reported:
  • Case: The temperature at the center of the FPGA lid.
  • FPGA Core: The temperature at the specified sensor on the FPGA core.
  • HSSI_x_y: The temperature of the specified high-speed serial interface (HSSI) die.
Sensor The digital thermal sensor (DTS) or thermal diode (TD) sensor reporting the temperature.
Temperature Target (°C) The calculated temperature for the target location and sensor, when the system is operating.

The monitor sensors report FPGA temperatures at the specified locations when the system is operating. These sensors may not necessarily be at the hottest locations on the die, and therefore can report values that are lower than the actual maximums in the design.

Thermal Page for Intel® Stratix® 10 Devices

Figure 26. Thermal Page of the Intel® FPGA PTC — Intel® Stratix® 10 Devices

In the above figure, input parameters are circled in blue and reporting fields are circled in red.

Table 26.  Input Parameter Information
Parameter Name Description
Calculation Mode Specifies the calculation mode for the thermal solver to use.
Apply Additional Margin

Specifies as a percentage, the amount of additional margin to apply to detailed thermal analysis results.

The default value is 0%. Valid values are 0–25%. The recommended margin for Intel® Stratix® 10 devices is 25%.

Consult your Intel Field Application Engineer (FAE) if you require additional guidance on margin power.

Note:
  1. Setting a non-zero margin causes the total power value on the Thermal page to be higher than the power reported elsewhere in the PTC.
  2. If you import a .ptc file from an earlier version of the Intel® FPGA PTC, which has the Apply Recommended Margin parameter set to Yes, the current version of the PTC interprets this as an Apply Additional Margin setting of 25%.
TSD Mode Specify the method by which offset temperatures are provided—such as from a thermal diode, or a digital temperature sensing mechanism.
Junction temperature, TJ (°C)

Specify the junction temperature for all dies in the package.

This field applies only when the selected Calculation mode value is Use a constant junction temperature.

Ambient Temp, TA (°C) Specify the temperature of the air that is cooling the device.
Max. Junction Temp, TJ-MAX (°C) Specify the maximum junction temperature that no part of any die in the package should exceed.
Cooling Solution ΨCA(°C/W) ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature.
Max. ΨJC(°C/W) ψJC is the thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. This field shows the maximum ΨJC among all dies, assuming the recommended ΨCA value above.

Table 27.  Temperature (°C)
Row Name Description
Max. Junction The maximum junction temperature that no part of any die in the package should exceed.
FPGA Core Junction The maximum junction temperature that no part of any die in the package should exceed.
Case The case temperature, which is the temperature at the top center of the integrated heat spreader, assuming the recommended ΨCA value listed above.
Ambient The temperature of the air that is cooling the device.
Table 28.  Power (W)
Row Name Description
Total Provides total power consumption of all dies in the package.
FPGA Core The total thermal power consumption of the main FPGA die containing core logic, assuming the recommended ΨCA value. This power is reported at the actual temperature of the core die, assuming the recommended ΨCA value. This temperature may be equal to the maximum junction temperature if the FPGA core die is at the highest temperature among all dies (also known as a hot spot). The FPGA core may also be at a lower temperature, if the hot spot is elsewhere in the package (i.e. on another die).
Transceiver HSSI_0_0 The total power consumption of HSSI_0_0, assuming the recommended ΨCA value. This power is reported at the actual temperature of the specific die, assuming the recommended ΨCA value above. This temperature may be equal to the maximum junction temperature if a specific die is the hot spot, or it may be at a lower temperature if the hot spot is elsewhere in the package.
Note: Each transceiver die in the package reports a small amount of static power even when no channels are used in the corresponding transceiver tile and transceiver rails (VCCR_GXB, VCCT_GXB, and VCCH_GXB) of that tile are grounded. This is an expected result.
HSSI_1_0
HSSI_2_0
HSSI_0_1
HSSI_1_1
HSSI_2_1
HBM Top The total thermal power consumption of HBM TOP or HBM BOT, assuming the recommended ΨCA value.

This power is reported at the actual temperature of the specific die, assuming the recommended ΨCA value above.

This temperature may be equal to the maximum junction temperature if a specific die is the hot spot, or it may be at a lower temperature if the hot spot is elsewhere in the package.

Bot
Table 29.  Recommended ψCA (°C/W)
Row Name Description
Recommended ψCA (°C/W) The thermal resistance between the center of the package integrated heat spreader and the ambient temperature, assuming the specific core temperature in the given table row. For each row, this is the ΨCA value that would cause the FPGA core junction temperature to be at the specific value for a given row.
Table 30.  ΨJC(°C/W)
Row Name Description
FPGA Core The thermal resistance between the main FPGA core die and the center of the package integrated heat spreader, assuming the recommended ΨCA value.
Transceiver HSSI_0_0 The thermal resistance between HSSI_0_0 and the center of the package integrated heat spreader, assuming the recommended ΨCA value.
HSSI_1_0
HSSI_2_0
HSSI_0_1
HSSI_1_1
HSSI_2_1
HBM TOP The thermal resistance between HBM TOP or HBM BOT and the center of the package integrated heat spreader, assuming the recommended ΨCA value.
BOT
Table 31.  TSD Offset (°C) ( Intel® Stratix® 10 Devices Only)
Row Name Description
FPGA Core The temperature difference between the hot spot on the main FPGA core and location of the thermal sensing diode (TSD) with the highest temperature reported using the Intel Temperature IP Sense software. (When the IP sense method is used to read the TSDs, all the TSD locations are read and the highest of these is reported.)
Transceiver HSSI_0_0 The temperature difference between the hot spot on the corresponding transceiver die and location of the thermal sensing diode (TSD) with the highest temperature reported using the Intel Temperature IP Sense software. (When the IP sense method is used to read the TSDs, all the TSD locations are read and the highest of these is reported.)

FPGA transceiver temperature = FPGA transceiver TSD temperature measured using the IP sense method + Transceiver TSD offset.

(If you are not using the Intel Temperature IP Sense software to read the TSD offsets, contact your Intel support representative for a workaround to get the correct TSD temperature.)

HSSI_1_0
HSSI_2_0
HSSI_0_1
HSSI_1_1
HSSI_2_1

For more information about HSSI_x_y locations, refer to the Physical Package Structure topic in AN 787: Intel® Stratix® 10 Thermal Modeling and Management.

Tables 26-30, above, show variations of thermal parameters and power consumption with changing junction temperature of the main FPGA core die. Three values are provided for each parameter. The Design Max column contains FPGA core temperature and other parameters assuming the recommended ΨCA value above. The -5°C column provides values of all parameters when FPGA core temperature is 5°C lower than in the Design Max column. Similarly, the +5°C column provides values of all parameters when FPGA core temperature is 5°C higher than in the Design Max column. It is important to realize that under the conditions in the +5°C column at least one part of one die in the package exceeds the requested maximum junction temperature, and may even exceed the maximum allowed value for the device. Therefore the values in the +5°C column should be used only as an estimate of power dependence on temperature for the purpose of computational fluid dynamic (CFD) simulation, and not for any other purpose

In extreme cases, such as thermal runaway, it may not be possible to calculate the values for +/- 5 degrees, in which case the Thermal worksheet displays the error message: ERROR: Could not calculate parameter variation with core temperature. Try adjusting TJ-MAX to obtain temperature-dependent parameters. When this error occurs, the recommended ΨCA value and all other values above are valid, but the table showing variation of thermal parameters and power consumption with changing junction temperature of the main FPGA core die contains some invalid values. As the error text indicates, adjusting the maximum junction temperature may allow the thermal solver to calculate this dependence, albeit at a different range of FPGA core temperatures than the usual range.

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