Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/21/2024
Public
Document Table of Contents

3.3. Read-During-Write (RDW)

In digital circuits, RDW occurs when a memory location (address) is accessed for both reading and writing data simultaneously.

This can lead to unpredictable behavior, as the read operation might capture the old data, the new data being written, or a mix of both, depending on the timing.

When using the M20K memory block in Quartus® Prime IP with RDW conflicts, you can configure the output behavior through two specific parameters:
  • Old Data: This ensures the read operation reflects the data present at the address before the write operation began.
  • Don't Care: The output value during RDW is unpredictable. Use this if the specific data value during the conflict isn't critical.

Separate Read and Write Clocks

For designs using separate read and write clocks, to avoid RDW conflicts, the write operation should change the address (on the rising edge of the write clock) to a different value than the read address before the rising edge of the read clock which starts the read operation.