Stratix® 10 Embedded Memory User Guide

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ID 683423
Date 10/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Embedded Memory Overview 2. Stratix® 10 Embedded Memory Architecture and Features 3. Stratix® 10 Embedded Memory Design Considerations 4. Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
1. Stratix® 10 Embedded Memory Overview x
1.1. Stratix® 10 Embedded Memory Features
2. Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Stratix® 10 Supported Embedded Memory IPs 2.11. Stratix® 10 Embedded Memory Clocking Modes 2.12. Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.8. True Dual Port Dual Clock Emulator x
2.8.1. Reducing the DCFIFO Depth
2.11. Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design 3.9. Resource and Timing Optimization Feature in MLAB Blocks 3.10. Consider the Memory Depth Setting 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs 4.2. eSRAM Intel® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. FIFO2 Intel® FPGA IP 4.5. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® FPGA IP x
4.2.1. Release Information for eSRAM Intel® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® FPGA IP Parameters 4.2.4. eSRAM Intel® FPGA IP Interface Signals 4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 Intel® FPGA IP x
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 Intel® FPGA IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 Intel® FPGA IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 Intel® FPGA IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines
4.5. Shift Register (RAM-based) Intel® FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Intel Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide

4.3.16. FIFO Intel® FPGA IP Parameters

Table 54.  FIFO Intel® FPGA IP Parameters DescriptionThis table lists the parameters for the FIFO Intel® FPGA IP core.
Parameter Legal Values Description
Parameter Settings: Width, Clk, Synchronization
How wide should the FIFO be? — Specifies the width of the data and q ports.
How deep should the FIFO be? Note: You could enter arbitrary values for width 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and 131072 Specifies the depth of the FIFO, which is always a power of 2.
Do you want a common clock for reading and writing the FIFO?
  • Yes, synchronize both reading and writing to 'clock'. Create one set of full/empty control signals.
  • No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for each clock.
—
Parameter Settings: SCFIFO Options
Would you like to disable any circuitry protection?
  • full
  • empty
  • usedw[] (number of words in FIFO).

    Note: You can use the MSB to generate a half full flag.

  • almost full becomes true when usedw[] is greater than or equal to
  • almost empty becomes true when usedw[] is less than
  • Asynchronous clear
  • Synchronous clear (flush the FIFO)
 On/Off —
Parameter Settings: DCFIFO 1
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for each clock., the following options are available:

Total latency, clock synchronization, metastability protection, area, and fmax options must be set as a group. Total latency is the sum of two write clock rising edges and the number of read clocks selected below.

Which option(s) is most important to the DCFIFO? (Read clk sync stages, metastability protection, area, fmax)

Which type of optimization do you want?
  • Lowest latency but requires synchronized clocks. 1 sync stage, no metastability protection, smallest size, good fmax.
  • Minimal setting for unsynchronized clocks. 2 sync stages, good metastability, medium size, good fmax.
  • Best metastability protection, best fmax, unsynchronized clocks. 3 or more sync stages, best metastability protection, largest size, best fmax.
Specify total latency, clock synchronization, metastability protection, area, and fmax.
  • Lowest latency but requires synchronized clocks—This option uses one synchronization stage with no metastability protection. It uses the smallest size and provides good fMAX. Select this option if the read and write clocks are related clocks.
  • Minimal setting for unsynchronized clocks—This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.
  • Best metastability protection, best fmax, unsynchronized clocks—This option uses three or more synchronization stages with the best metastability protection. It uses the largest size but gives the best fMAX.
More options When you select Best metastability protection, best fmax, unsynchronized clock, the following option is available:
  • How many sync stages?
 3, 4, 5, 6, 7, 8, and 9 Specifies the number synchronization stages.
Timing Constraint
  • Generate SDC file and disable embedded timing constraint
On/Off Generate a SDC file with correct timing constraints. Embedded set_false_path assignment is disabled. The new timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay. For more information on the timing constraint usage, refer to user guide.
Parameter Settings: DCFIFO 2
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for each clock., the following options are available:

Which optional output control signals do you want?

usedw[] is the number of words in the FIFO.

 On/Off —
Read-side
  • full
  • empty
  • usedw[]

Note: These signals are synchronous to 'rdclk'.

 —
Write-side
  • full
  • empty
  • usedw[]

Note: These signals are synchronous to 'wrclk'.

 —
More options
  • Add an extra MSB to usedw port(s). Note: You can use the MSB to generate a half-full flag.
  • Asynchronous clear
  • Add circuit to synchronize 'aclr' input with 'wrclk'
  • Add circuit to synchronize 'aclr' input with 'rdclk'
On/Off —
Parameter Settings: Rdreq Option, Blk Type
Which kind of read access do you want with the 'rdreq' signal?
  • Normal FIFO mode.
  • Show-ahead synchronous FIFO mode.
Specifies whether the FIFO is in Legacy mode or in Show-ahead mode.
  • Normal FIFO mode—The data becomes available after 'rdreq is asserted. 'rdreq' acts as a read request.
  • Show-ahead synchronous FIFO mode—The data becomes available before 'rdreq' is asserted. 'rdreq' acts as a read acknowledge. Note: This mode suffers a performance penalty.
What should the memory block type be?
  • Auto
  • MLAB
  • M20K
  • M144K
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to: Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and 131072 Specifies the maximum block depth in words.
Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9. On/Off —
Parameter Settings: Optimization, Circuitry Protection
Would you like to register the output to maximize performance but use more area?
  • Yes (best speed)
  • No (smallest area)
Specifies whether to register the RAM output.
Implement FIFO storage with logic cells only, even if the device contains memory blocks. On/Off Specifies whether to implement FIFO storage with logic cells only.
Would you like to disable any circuitry protection (overflow checking and underflow checking)?
If not required, overflow and underflow checking can be disabled to improve performance.
  • Disable overflow checking. Writing to a full FIFO corrupts contents.
  • Disable underflow checking. Reading from an empty FIFO corrupts contents
 On/Off Specifies whether to disable any circuitry protection for overflow
Would you like to enable ECC?
  • Enable error checking and correcting (ECC)
On/Off Specifies whether to enable error checking and correcting feature.
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