Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/21/2024
Public
Document Table of Contents

2.2. Address Clock Enable Support

The Stratix® 10 embedded memory blocks support address clock enable. When you enable address clock enable (addressstall = 1), it holds the previous address value.
Note: Only simple dual-port mode supports this feature.

When you configure the memory blocks in dual-port mode, each port has its own independent address clock enable.

Figure 2.  Address Clock Enable This figure shows an address clock enable block diagram.


Figure 3.  Address Clock Enable During Read Cycle This figure shows the address clock enable behavior during read cycle.


Figure 4.  Address Clock Enable During Write Cycle This figure shows the address clock enable behavior during write cycle.