Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3. FIFO Intel® FPGA IP

Intel® provides FIFO Intel® FPGA IP through the parameterizable single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) functions.
The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains.
The specific names of the FIFO functions are as follows:
  • SCFIFO: single-clock FIFO
  • DCFIFO: dual-clock FIFO (supports same port widths for input and output data)
  • DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output data)
Note: The term "DCFIFO" refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS IPs, unless specified.