FIFO Intel® FPGA IP User Guide

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ID 683522
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

FIFO Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 18.0
Intel® provides FIFO Intel® FPGA IP core through the parameterizable single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) functions. The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains.

The specific names of the FIFO functions are as follows:

  • SCFIFO: single-clock FIFO
  • DCFIFO: dual-clock FIFO (supports same port widths for input and output data)
  • DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output data)
Note: The term “DCFIFO” refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS functions, unless specified.

Section Content
Configuration Methods
Specifications
FIFO Functional Timing Requirements
SCFIFO ALMOST_EMPTY Functional Timing
FIFO Output Status Flag and Latency
FIFO Metastability Protection and Related Options
FIFO Synchronous Clear and Asynchronous Clear Effect
SCFIFO and DCFIFO Show-Ahead Mode
Different Input and Output Width
DCFIFO Timing Constraint Setting
Coding Example for Manual Instantiation
Design Example
Gray-Code Counter Transfer at the Clock Domain Crossing
Guidelines for Embedded Memory ECC Feature
FIFO Intel FPGA IP User Guide Archives
Document Revision History for the FIFO Intel FPGA IP User Guide

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