Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.8.1. RAM and ROM Parameter Settings

Table 29.   Parameters for altera_syncram Use the parameter list when editing the design file manually.
Name Legal Values Description
operation_mode

SINGLE_PORT

DUAL_PORT

BIDIR_DUAL_PORT

QUAD_PORT

ROM

Operation mode of the memory block.
width_a Data width of port A.
widthad_a Address width of port A.
widthad2_a   Address 2 width of port A.
numwords_a Number of data words in the memory block for port A.
outdata_reg_a

UNREGISTERED

CLOCK1

CLOCK0

Clock for the data output registers of port A.
outdata_aclr_a

NONE

CLEAR1

CLEAR0

Asynchronous clear for data output registers of port A. When the outdata_reg_a parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
outdata_sclr_a

NONE

SCLEAR

Synchronous clear for data output registers of port A. When the outdata_reg_a parameter is set to NONE, this parameter specifies the clearing parameter for the output latch.
address_aclr_a

NONE

Option to clear the address input registers of port A.
width_byteena_a Width of the byte-enable bus of port A. The width must be equal to the value of width_a divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
width_b Data width of port B.
widthad_b Address width of port B.
widthad2_b Address 2 width of port B.
numwords_b Number of data words in the memory block for port B.
outdata_reg_b

UNREGISTERED

CLOCK1

CLOCK0

Clock for the data output registers of port B.
indata_reg_b

CLOCK1

CLOCK0

Clock for the data input registers of port B.
address_reg_b

CLOCK1

CLOCK0

Clock for the address registers of port B.
byteena_reg_b

CLOCK1

CLOCK0

Clock for the byte-enable registers of port B.
outdata_aclr_b

NONE

CLEAR1

CLEAR0

Asynchronous clear for data output registers of port B. When the outdata_reg_b parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
outdata_sclr_b

NONE

SCLEAR

Synchronous clear for data output registers of port B. When the outdata_reg_b parameter is set to NONE, this parameter specifies the clearing parameter for the output latch.
address_aclr_b

NONE

Option to clear the address input registers of port B.
width_byteena_b Width of the byte-enable bus of port B. The width must be equal to the value of width_b divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
intended_device_family

“Stratix 10”

Parameter used for simulation purpose.
ram_block_type

AUTO

M20K

MLAB

The memory block type.
byte_size

5

8

9

10

The byte size for the byte-enable mode.
read_during_write_mode_mixed_ports

DONT_CARE

CONSTRAINT_DONT_CARE

NEW_DATA

OLD_DATA

NEW_A_OLD_B

The behavior for the read-during-write mode.
  • The default value is DONT_CARE.
  • The value of NEW_DATA is supported only when the read address and output data are registered by the write clock in the LUTRAM mode.
  • The value of CONSTRAINED_DONT_CARE is supported only in the LUTRAM mode.
  • The value of NEW_A_OLD_B is supported only when the operation_mode parameter is set to QUAD_PORT.
init_file

*.mif

*.hex

The initialization file.
init_file_layout

PORT_A

PORT_B
The layout of the initialization file.
maximum_depth The depth of the memory block slices.
clock_enable_input_a

NORMAL

BYPASS

The clock enable for the input registers of port A.
clock_enable_output_a

NORMAL

BYPASS

The clock enable for the output registers of port A.
clock_enable_input_b

NORMAL

BYPASS

The clock enable for the input registers of port B.
clock_enable_output_b

NORMAL

BYPASS

The clock enable for the output registers of port B.
read_during_write_mode_port_a

NEW_DATA_NO_NBE_READ

NEW_DATA_WITH_NBE_READ

OLD_DATA

DONT_CARE

The read-during-write behavior for port A.
read_during_write_mode_port_b

NEW_DATA_NO_NBE_READ

NEW_DATA_WITH_NBE_READ

OLD_DATA

DONT_CARE

The read-during-write behavior for port B.
enable_ecc

TRUE

FALSE

Enables or disables the ECC feature.
ecc_pipeline_stage_enabled

TRUE

FALSE

  • Specifies whether to enable ECC Pipeline Registers before the output decoder to achieve the same performance as non-ECC mode at the expense of one cycle of latency.
  • The parameter enable_ecc must set to TRUE if this parameter is set to TRUE.
  • The parameter outdata_reg_b cannot set to UNREGISTERED if this parameter is set to TRUE.
  • The default value is FALSE.
enable_ecc_encoder_bypass

TRUE

FALSE

Enables or disables the ECC Encoder Bypass feature.
  • The parameter enable_ecc must set to TRUE if this parameter is set to TRUE.
enable_coherent_read

TRUE

FALSE

Enables or disables the coherent read feature.
  • The default value is FALSE.
enable_force_to_zero

TRUE

FALSE

Enables or disables the Force-to-Zero feature.
  • The default value is FALSE.
width_eccencparity 8 The width of the eccencparity signal.
optimization_option

AUTO

Specifies how the RAM block would be optimized.
  • If AUTO is selected, the fitter determines whether the RAM block is in High_Speed or Low_Power mode.
  • The RAM block type must be M20K when High_Speed or Low_Power is selected.