Intel® Stratix® 10 Embedded Memory User Guide

Download PDF
ID 683423
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Embedded Memory Overview 2. Intel® Stratix® 10 Embedded Memory Architecture and Features 3. Intel® Stratix® 10 Embedded Memory Design Considerations 4. Intel® Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Intel® Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide
1. Intel® Stratix® 10 Embedded Memory Overview x
1.1. Intel® Stratix® 10 Embedded Memory Features
2. Intel® Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Intel® Stratix® 10 Supported Embedded Memory IPs 2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes 2.12. Intel® Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Intel® Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Intel® Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Intel® Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs 4.2. eSRAM Intel® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. FIFO2 Intel® FPGA IP 4.5. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® FPGA IP x
4.2.1. Release Information for eSRAM Intel® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® FPGA IP Parameters 4.2.4. eSRAM Intel® FPGA IP Interface Signals 4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 Intel® FPGA IP x
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 Intel® FPGA IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 Intel® FPGA IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 Intel® FPGA IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines
4.5. Shift Register (RAM-based) Intel® FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Intel Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Intel® Stratix® 10 Embedded Memory Overview
2. Intel® Stratix® 10 Embedded Memory Architecture and Features
3. Intel® Stratix® 10 Embedded Memory Design Considerations
4. Intel® Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Intel® Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide

4.2.2.2. eSRAM Usage Model

The eSRAM configuration is deemed static after FPGA configuration. You cannot reconfigure the eSRAM after it enters user mode.

All 8 memory channels have an interface to a shared set of 3 fabric sectors. The fitter chooses which sector interfaces with core logic because not all the sectors are available for each eSRAM.

The reference clock (refclk) is only support LVDS standard. When setting an instance assignment, use the correct standard for refclk. An instance assignment must be set to use the correct standard for refclk: 

set_instance_assignment -name IO_STANDARD LVDS -to refclk
Figure 30. eSRAM Interface With Core Logic
There is a maximum of 17 address bits available. Address bits [10:0] are the 11 bits used to target the 2K entries in a bank. Address bits [16:11] are the 6 bits used to target a certain bank in a channel. Because there are only 42 banks in a channel, the threshold address you can target is [16:11] = 6'b101001 (41st bank relative to the 0th Bank).
Note: eSRAM bits cannot be reset while in user mode and hence do not have a reset requirement.

Each of the 8 memory channels that make up an eSRAM can power down unused banks. You are responsible for selecting the desired capacity in the eSRAM Intel® FPGA IP as the unused banks are powered down by default.

Level Two Title