Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.6.1. FIFO2 Parameter Settings

Table 60.  FIFO2 Parameters Description
Parameter Description
DATAWIDTH FIFO Write and Read Data Width.

The user width granularity is as below, depending on the RAM block type:

  • M20K: 32n; where n = 1 to 128
  • MLAB: 20n; where n = 1 to 205

This allows up to 4096 bit width which should be more than enough for different applications.

All unused bits (for example, bits that do not carry any information) should be tied-off. For instance, if the user data width were 20-bit and M20K RAM block is used, there would be 12 unused bits to be tied-off.

The default value for n is 1.

SCFIFO_MODE SCFIFO Mode.

Specify whether the FIFO should operate in SCFIFO mode, in which the clock crossing logic structure between Write and Read clock domains shall be removed.

  • 1— SCFIFO mode
  • 0 (default)—DCFIFO mode
RAM_BLK_TYPE RAM Block Type.

Specify the embedded RAM blocks to be used as the main FIFO storage.

  • "M20K" (default)—Use M20K
  • "MLAB"—Use MLAB
USE_ACLR_PORT Use Asynchronous Clear Port.

Specify whether the asynchronous reset ports (for example, w_aclr and r_aclr) of the IP should have effect.

  • 1—Ports are used to asynchronously reset the IP
  • 0 (default)—Ports are not used and have no effect
WRPTR_GRY_SYNC_CHAIN_LEN Write Gray-Code Pointer Synchronizer Chain Length.

Specify the number of flop stages used to synchronize Write Gray-Code Pointer to the r_clk domain.

  • 3 (default)—Use 3-stage synchronizer
  • 4—Use 4-stage synchronizer
RDPTR_GRY_SYNC_CHAIN_LEN Read Gray-Code Pointer Synchronizer Chain Length.

Specify the number of flop stages used to synchronize Read Gray-Code Pointer to the w_clk domain.

  • 3 (default)—Use 3-stage synchronizer
  • 4—Use 4-stage synchronizer
RAM_WRPTR_DUPLICATE RAM Write Address Duplication.

Specify whether RAM Write Address and associated logic (where appropriate) should be duplicated per RAM block.

  • 1—Enable per RAM block preserve/duplication. This may increase Fmax at the expense of resources
  • 0 (default)—Do not enable per RAM block preserve/duplication. You can determine which registers should be duplicated through assignment.
RAM_RDPTR_DUPLICATE RAM Read Address Duplication.

Specify whether RAM Read Address (and associated logic where appropriate should be duplicated per RAM block. U

  • 1—Enable per RAM block preserve/duplication. This may increase Fmax at the expense of resources
  • 0 (default)—Do not enable per RAM block preserve/duplication. You can determine which registers should be duplicated through assignment.