Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 4/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.7.2.1. Reference Design Components

Figure 5. Reference Design Block Diagram
Table 7.  Reference Design Components Descriptions
Component Description
JTAG UART Intel® FPGA IP Enables communication between the Nios® II processor and the host computer.
Nios® II Processor Runs application program by executing data and instruction.
On-Chip Memory Intel® FPGA IP
  • Stores code and data.
  • Connects the Nios® II instruction master to the on-chip memory block.
Generic Serial Flash Interface Intel® FPGA IP Controls vendor-independent flash device to perform flash interaction.