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1.1. Release Information
1.2. Device Family Support
1.3. Signals
1.4. Parameters
1.5. Register Map
1.6. Using Generic Serial Flash Interface Intel® FPGA IP
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP
1.9. Nios II HAL Driver
1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives
1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
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1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP
This section provides information to use the Generic Serial Flash Interface (GSFI) Intel® FPGA IP registers (Table 4. Register Map) to perform flash access. This example design performs flash access to the Active Serial (AS) configuration flash in control block-based devices. To begin, you must build the Platform Designer system as shown in Figure 8. Example of Creating Flash Access Using the Generic Serial Flash Interface Intel FPGA IP.
Key Components:
- Clock and Reset Bridge Intel® FPGA IP
- Generic Serial Flash Interface Intel® FPGA IP
- JTAG to Avalon Master Bridge Intel® FPGA IP
For more information about other components, refer to the Embedded Peripherals IP User Guide.
Figure 8. Example of Creating Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP
Note: To access the AS configuration flash, set the MSEL pins of the FPGA devices to the AS configuration mode. To access the general purpose QSPI flash, enable the Disable Dedicated Active Serial Interface and Enable SPI Pins Interface parameter of this IP.
For SDM-based devices, use the Mailbox Client Intel FPGA IP to access the AS configuration flash.
For Intel® MAX® 10 devices, enable the Disable Dedicated Active Serial Interface and Enable SPI Pins Interface parameter of this IP to access the general purpose QSPI flash.
As per the Address Map shown in the figure below, the GSFI Intel® FPGA IP register map spans within the address 0x8000000 to 0x80000ff, whereas the flash memory (1024 Mb) spans from 0x0 to 0x7ffffff. These addresses are crucial to access the correct register or flash memory space.
Figure 9. Address Map
In this example, System Console is used to access the GSFI Intel® FPGA IP and flash memory. The System Console utilizes the JTAG to Avalon Master Bridge Intel® FPGA IP along with a TCL script.
Example : Sample .tcl script
#set GSFI CSR base address and register map according to Platform Designer
#system
set base 0x8000000
set control_register [expr {$base + 0x0}]
set spi_clock_baud_rate_register [expr {$base + 0x4}]
set cs_delay_setting_register [expr {$base + 0x8}]
set read_capturing_register [expr {$base + 0xc}]
set operating_protocols_setting [expr {$base + 0x10}]
set read_instr [expr {$base + 0x14}]
set write_instr [expr {$base + 0x18}]
set flash_cmd_setting [expr {$base + 0x1c}]
set flash_cmd_ctrl [expr {$base + 0x20}]
set flash_cmd_addr_register [expr {$base + 0x24}]
set flash_cmd_write_data_0 [expr {$base + 0x28}]
set flash_cmd_write_data_1 [expr {$base + 0x2c}]
set flash_cmd_read_data_0 [expr {$base + 0x30}]
set flash_cmd_read_data_1 [expr {$base + 0x34}]
#claims JTAG to Avalon Master Bridge service
set mp [claim_service master [lindex [get_service_paths master] 0] top]
#print the value of Control Register
set reg [master_read_32 $mp $control_register 0x1]
puts "Control Register : $reg"
#you may perform the flash operation here
#close JTAG to Avalon Master Bridge service
close_service master $mp
For more information on System Console services and commands, refer to the Analyzing and Debugging Designs with System Console.
Flash operations are divided into several categories. Example of operations, registers to use, and sample .tcl scripts for each category are provided.