Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/20/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Intel® Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Nios II HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.04.20 22.1 20.1.1 Corrected the Reserved Bit value for the following registers in Table: Register Map:
  • From 31:8 to 31:9 for Control Register.
  • From 31:14 to 31:13 for Read Instruction Register.
2022.04.07 22.1 20.1.1 Updated description for Flash Access Using the Generic Serial Flash Interface Intel FPGA IP section with additional information.
2021.11.09 21.2 20.1.1 Updated CS Delay Setting Register in Register Map topic.
2021.06.21 21.2 20.1.1
  • Updated Device Family Support.
  • Updated Nios® II HAL Driver:
    • Updated the intel_gsfi_get_info description in Table: intel_gsfi_get_info.
    • Updated the intel_gsfi_read description in Table: intel_gsfi_read.
    • Nios® II HAL Driver
  • Removed the Driver API Application topic.
  • Updated Figure: Reference Design Block Diagram.
2021.03.29 21.1 20.1.1
  • Added the following sections:
    • Nios II HAL Drivers
    • Driver API
    • Driver API Application
  • Corrected the default value for dummy cycles from 0xA to 0x0 in Table: Register Map.
  • Updated the steps in the Perform Page Program (Extended Mode) and Perform 4-byte Quad Input Fast Program (Quad SPI Mode) examples in Program Flash.
2020.09.28 20.3 20.0.0
  • Added a new register setting—tSHSL.
  • Added a new section—Constraining the I/O Pins.
  • Updated the description for Enable flash simulation model in Table: Parameter Settings.
  • Removed Control Status Register Operations.
  • Updated the following topics:
    • Generic Serial Flash Interface Intel® FPGA IP User Guide
    • Release Information
    • Memory Operations
  • Updated the Hardware and Software Requirements of the Generic Serial Flash Interface Intel® FPGA IP Reference Design section.
  • Updated the description of On-Chip Memory Intel® FPGA IP in Table: Reference Design Components Descriptions.
  • Updated Creating Nios® II Hardware System:
    • Updated the description in step 7c.
    • Updated Figure: Completed Platform Designer Connection.
  • Made minor editorial updates through out the document.
2020.05.08 20.1 19.2.1
  • Added new sections—Release Information and Control Status Register Byte Enable.
  • Updated Table: Parameter Settings to include a new parameter—Use byteenable for CSR.
  • Added a new signal—avl_csr_byteenable.
  • Updated Figure: Signal Block Diagram.
  • Updated the note to the Device Family Support topic.
2020.04.13 19.4 19.1.1
  • Renamed document title as Generic Serial Flash Interface Intel® FPGA IP User Guide
  • Added the Byte Enabling section.
  • Added a note to the Device Family Support topic.
  • Updated the Memory Operations topic.
  • Updated for latest branding standards.
2019.11.27 19.3 19.1 Added a note to the Memory Operations topic.
2019.09.30 19.3 19.1
  • Added support for Intel® Agilex™ devices.
  • Updated the Device Family Support topic.
  • Made minor editorial updates to the document.
2018.11.09 18.1 18.1
  • Added the Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP Core section.
  • Added the Generic Serial Flash Interface Intel® FPGA IP Core User Guide Archives section.
  • Updated the Generic Serial Flash Interface Intel® FPGA IP Core User Guide section to provide more information on the Generic Serial Flash Interface Intel® FPGA IP core.
  • Updated the signal names of the Signal Block Diagram figure.
  • Updated the Conduit Interface signal names in the Ports Description table.
  • Updated the description of the write opcode field name of the write instruction register in the Register Map table.
2018.05.16 18.0 18.0
  • Updated the Generic Serial Flash Interface Intel FPGA IP Core Reference Design Files link.
  • Added Flash Command Address Register in the Register Map.
2018.05.07 18.0 18.0 Initial release.
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