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1.1. Release Information
1.2. Device Family Support
1.3. Signals
1.4. Parameters
1.5. Register Map
1.6. Using Generic Serial Flash Interface Intel® FPGA IP
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP
1.9. Nios II HAL Driver
1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives
1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
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1.4. Parameters
Parameter | Legal Values | Descriptions |
---|---|---|
Device Density | 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 | Density of the flash device used in Mb. |
Disable dedicated Active Serial interface | — | Routes the signals to the top level of your design. Enable this when you want to include the Serial Flash Loader Intel FPGA IP in your design. |
Enable SPI pins interface | — | Translates the signals to the SPI pin interface. |
Number of Chip Select used | 1 2 3 |
Selects the number of chip select connected to the flash. |
Enable flash simulation model | — | Uses the default EPCQ1024 simulation model for simulation. When disabled, refer to AN-720: Simulating the ASMI Block in Your Design for creating a wrapper to use with other flash simulation model. |
Use byteenable for CSR | — | Turns on byteenable for CSR writedata interface. |
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