Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/20/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Intel® Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Nios II HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.2. Device Family Support

The Generic Serial Flash Interface IP is supported in the following devices:

  • Intel® Agilex™ 2 3 4
  • Intel® Stratix® 10 2 3
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Cyclone® 10 LP
  • Intel® MAX® 10 (For general purpose memory only) 2
  • Stratix® V
  • Arria® V
  • Cyclone® V
  • Stratix® IV
  • Cyclone® IV
  • Arria® II
Related Information
2 Export the flash pin by enabling the Enable SPI pins interface parameter of this IP.
3 The IP can only access flash that is connected to FPGA GPIO pins. The IP cannot be used to access flash that is connected to SDM for configuration purpose.
4 The exported conduit pins, which have different Output Enable (OE) signals, should not be placed in the same x4 DQ group. Error(175005) may trigger due to the OE conflict during compilation. Refer to the Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide and the KDB Answer Error (175005): Could not find a location with: GPIO_SHARED_NOE0 of (locations affected) for more information.
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