Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/20/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Intel® Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash Perform Page Program (Extended Mode) Perform 4-byte Quad Input Fast Program (Quad SPI Mode)
1.9. Nios II HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.8.6. Program Flash

The following registers are used to perform program flash:

  • Operating protocols setting
  • Control register
  • Write instruction

Perform Page Program (Extended Mode)

proc page_program { } {
global mp operating_protocols_setting control_register write_instr
master_write_32 $mp $operating_protocols_setting 0x00000000
master_write_32 $mp $control_register 0x00000001
master_write_32 $mp $write_instr 0x00007002
master_write_32 $mp 0x00001000 0x1234abcd
 }

To perform the page program for the extended mode, follow these steps:

  1. Define the global variables.
  2. Write to the operating protocols setting register to set the transfer mode of the program operation. In this example, the transfer mode for read is (1-1-1).
    1. Set the instruction transfer mode [1:0] to 0, write address transfer mode [5:4] to 0, and write data in transfer mode [9:8] to 0.
  3. Write to the control register to choose the byte addressing mode of the write operation.
    1. This example is using the 3-byte addressing mode. Set bit 8 to 0.
  4. Write to the write instruction register to customize the program operation.
    1. Set the write operation code [7:0] to 02 as 02h is the operation code for page program.
    2. Set the polling operation code [15:8] to 70 as 70h is the operation code for the read flag status register. After completing the write operation, the IP core releases the wait request of the Avalon® memory-mapped interface. For the flash that does not have the read flag status register, you can use the read status register (05h).
  5. After setting the registers, you can start to program the memory into the address.
    1. In this example, 1234abcdh is written to the memory address 0x00001000.

Perform 4-byte Quad Input Fast Program (Quad SPI Mode)

proc fourbyte_quad_input_fast_program { } {
global mp operating_protocols_setting control_register write_instr
master_write_32 $mp $operating_protocols_setting 0x00000222
master_write_32 $mp $control_register 0x00000101
master_write_32 $mp $write_instr 0x00007034
master_write_32 $mp 0x00002000 0xabcd1234
}

To perform the 4-byte quad input fast program, follow these steps:

  1. Define the global variables.
  2. Write to the operating protocols setting register to set the transfer mode of the program operation. In this example, the transfer mode for 4-byte quad input fast program is (4-4-4).
    1. Set the instruction transfer mode [1:0] to 2, write address transfer mode [5:4] to 2, and write data in transfer mode [9:8] to 2.
  3. Write to the control register to choose the byte addressing mode of the write operation.
    1. This example is using the 4-byte addressing mode. Set bit 8 to 1.
  4. Write to the write instruction register to customize the program operation.
    1. Set the write operation code [7:0] to 34 as 34h is the operation code for the 4-byte quad input fast program.
    2. Set the polling operation code [15:8] to 70 as 70h is the operation code for the read flag status register. After completing the write operation, the IP core releases the wait request of the Avalon® memory-mapped interface. For the flash that does not have the read flag status register, you can use the read status register (05h).
  5. After setting the registers, you can start to program the memory into the address.
    1. In this example, 1234abcdh is written to the memory address 0x00002000.
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