AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

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ID 683409
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 6: Defining Personas Step 7: Creating Revisions Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script Step 9: Running the Hierarchical Partial Reconfiguration Flow Script Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 7: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning
Level Two Title