AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

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ID 683409
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 6: Defining Personas Step 7: Creating Revisions Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script Step 9: Running the Hierarchical Partial Reconfiguration Flow Script Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 7: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core

Use the Intel® Arria® 10 Partial Reconfiguration Controller IP core to reconfigure the PR partition. This IP core uses JTAG to reconfigure the PR partition. To add the Intel® Arria® 10 Partial Reconfiguration Controller IP core to your Intel® Quartus® Prime project:
  1. Type Partial Reconfiguration in the IP catalog.
  2. To launch the IP Parameter Editor Pro window, select the Intel® Arria® 10 Partial Reconfiguration Controller IP core from the IP library, and click Add.
  3. In the New IP Variant dialog box, type pr_ip as the file name and click Create. Use the default parameterization for pr_ip. Ensure that the Enable JTAG debug mode and Enable freeze interface options are turned on, and Enable Avalon-MM slave interface option is turned off.
    Figure 7.  Intel® Arria® 10 Partial Reconfiguration Controller IP Core Parameters
  4. Click Finish, and exit the parameter editor without generating the system. Intel® Quartus® Prime software creates the pr_ip.ip IP variation file, and adds the file to the blinking_led project.
Note:
  1. If you are copying the pr_ip.ip file from the hpr folder, manually edit the blinking_led.qsf file to include the following line:
    set_global_assignment -name IP_FILE pr_ip.ip
  2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration IP core.
    Note: To detect the clocks, the SDC file for the PR IP must follow any SDC that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or SDC files used to create these clocks in the QSF file for your Intel® Quartus® Prime project revision. For more information, refer to Timing Constraints section in the Partial Reconfiguration IP Core User Guide.

Section Content
Updating the Top-Level Design

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