Visible to Intel only — GUID: jtb1488919246842
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core
Step 6: Defining Personas
Step 7: Creating Revisions
Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script
Step 9: Running the Hierarchical Partial Reconfiguration Flow Script
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: jtb1488919246842
Ixiasoft
Modifying an Existing Persona
You can change an existing persona, even after fully compiling the base revision.
For example, to cause the blinking_led_child_slow persona to blink even slower:
- In the blinking_led_child_slow.sv file, modify the COUNTER_TAP parameter from 27 to 28.
- To re-synthesize and re-implement this persona, you must recompile all the synthesis-only revisions and implementation revisions affected by the change. Modify the setup.tcl script to include the following lines:
define_project blinking_led define_base_revision blinking_led define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_partition \ -source_rev_name blinking_led_child_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_alpha \ -source_partition pr_parent_partition \ -source_snapshot final define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_partition \ -source_rev_name blinking_led_child_slow \ -source_partition root_partition \ -source_snapshot synthesized define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_parent_partition \ -source_rev_name blinking_led_pr_delta \ -source_partition pr_parent_partition \ -source_snapshot final
Note: When defining the pr_parent_parition for blinking_led_pr_delta revision, you import the final snapshot of that persona for implementation. As a result, the implementation of the parent partition logic remains the same, while modifying and implementing the corresponding child partition.This command re-synthesizes the blinking_led_child_slow synthesis revision, and then runs the PR implementation compile using blinking_led_pr_bravo. - To perform compilation of the synthesis-only revisions, run the following command:
quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script \ a10_hier_partial_reconfig/setup.tcl -all_syn
This command does not recompile the base revision.
- To perform compilation of the implementation revisions, run the following command:
quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script \ a10_hier_partial_reconfig/setup.tcl -all_impl
This command does not recompile the base revision.
- Follow the steps in Step 10: Programming the Board to program the resulting RBF file into the FPGA.
Note: To avoid running the entire flow for every revision, define the synthesis-only revisions and implementation revisions in the setup.tcl script, and run the script.