AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

Download PDF
ID 683409
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 6: Defining Personas Step 7: Creating Revisions Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script Step 9: Running the Hierarchical Partial Reconfiguration Flow Script Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 7: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:
  1. Create a directory in your working environment, a10_soc_devkit_blinking_led_hpr.
  2. Copy the downloaded tutorials/a10_soc_devkit_blinking_led_hpr/flat sub-folder to the directory, a10_soc_devkit_blinking_led_hpr.
  3. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
  4. To compile the flat design, click Processing > Start Compilation.
Level Two Title